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Technology Stocks : Applied Materials No-Politics Thread (AMAT) -- Ignore unavailable to you. Want to Upgrade?

To: Cary Salsberg who wrote (9057)	2/27/2004 12:35:13 PM
From: Kirk ©	Read Replies (1) \| Respond to of 25522

With the same design rules except diagonal routing, you might get a 20% or 30% gain in area efficiency. Thus more chips per wafer. Remember, this is an estimate.... Perhaps only 5 or 10% on some chips. I've never designed a 7 layer digital chip, I was an analog designer who did SOME digital for control function, but I've heard the loss is huge. As you say, you also get some performance gain due to shorter distances for electrons to travel hence better power delay products.