Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: TigerPaw who wrote (177961)	5/13/2004 7:27:41 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 186894

TP, The OS just doesn't know if memory is shared or not without checking each access. The OS has nothing to do with the MESI cache protocol. If one processor has a cacheline in Modified state, it can continually update the data in that cacheline as long as no other processor tries to access that cacheline. Same thing if the processor has two cores; both cores can access that cacheline without sending any coherency checks across the bus, because the Modified state guarantees that the processor is the sole owner of the cacheline. Of course, once the OS assigns two tasks that share memory to two different physical processors, then you'll have bus traffic, but your answer implies that there will be bus traffic even if the two tasks are assigned to different cores on the same processor. This is not the case. Tenchusatsu