Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (123644)	6/14/2004 3:08:22 PM
From: Joe NYC	Read Replies (1) \| Respond to of 275872

Petz, Intel will NOT be successful in killing x86 because of two indisuputable FACTS: 1. there is nothing computationally limiting in the x86 ISA with AMD64 extensions. 2. for a given amount of silicon, x86 is more efficient Installed base of existing software is probably bigger than any hardware issue, and will be the deciding factor, IMO. As far as #2, the Itanium core itself may not be that big, but on its own (without OOO) it has to have a lot of cache to be competitive. Joe

To: Petz who wrote (123644)	6/14/2004 9:43:53 PM
From: Joe NYC	Read Replies (1) \| Respond to of 275872

Petz, 1a. There is no reason an x86 CPU can't have a 4-input floating point pipeline like Itanium, or 6, or 8. And actually, anything >4 would do an Itanium no good, unless it is redesigned to be an OOO processor, which, as I said, pretty much defeats the purpose of the explicit parallellism. I came across this post from a guy who used to work for AMD, which makes it sound that FPU was borrowed from K7 (if my understanding is correct) to cut down on work needed. aceshardware.com FPU may be due for a significant overhaul in K9. Ability to better take advantage of potential parallelism (in FP)seems almost like a low hanging fruit. Joe