To: Biomaven who wrote (123959 ) 6/17/2004 8:06:27 AM From: fyodor_ Respond to of 275872 Biomaven: So which fits the current situation better - that scenario you just gave or the one at the other end of the spectrum, where they are demand-constrained at the lower end, and so can't produce enough high-end parts without over-producing low-end processors? I think the initial step must be to determine how many different cores AMD are actually producing. Only then can one look at pricing, availability, overclockability etc. and reasonably try to reach some conclusions as to what is going on. Let's look at A64 first: AthlonFX: 128bit memory (unbuffered DIMMs), 1MB L2 cache Opteron 1xx, 2xx, 8xx: 128bit memory (registered DIMMs), 1MB L2 cache Athlon64-M: 64bit memory (unbuffered DIMMs), 1MB L2 cache Athlon64: 64bit memory (unbuffered DIMMs), 512kB L2 cache My WAG would be that there are actually at least two, and quite possibly three, different cores here: core 1) Athlon64-M, AthlonFX core 2) Athlon64 "plain" core 3) Opteron where 1 and 3 could possibly be lumped together. I seriously doubt that AMD is wasting large amounts of valuable die space by disabling half the cache on the 1MB chips, so there would certainly need to be at least two different cores: One with 512kB L2 and one with 1MB L2 cache. The width of the memory controller does not really present much of an issue, IMHO. The big question in my opinion is whether Opterons represent a different core altogether. Since they can only use registered DIMMs, it would seem that their memory controller is different somehow. Additionally, they have more HyperTransport channels (well, the 2xx and 8xx models do). The 1xx model could possibly be covered by the "normal" 1MB L2 cache core, but considering the price premium on these parts, it wouldn't really matter much. In the end, though, I really don't have the necessary knowledge to do anything but WAG on whether there are two or three different cores. Perhaps someone more technically inclined could educate us as to whether the differences between the memory controllers and number of HyperTransport channels would be enough to warrant a third die? -fyo