Micron on the advantages of stacking Part 1
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Gary Cheng, Jack Lu and Stephen Taylor, DigiTimes.com, Taipei [Tuesday 14 September 2004]
With respect to a given lithography node – whether it’s 0.11- or 0.13-micron – both stack and trench processes are implementing 8F² technology. However, the various suppliers do not use standardized nomenclature to describe their technology nodes, and the actual technology nodes used depend on the companies’ internal lithography roadmaps.
This is the first section of a two-part interview. The second section will follow tomorrow.
Table 1: Comparison of 512Mb DDR die
Manufacturer
Micron (6F²)
Micron (6F²)
Infineon
Samsung
Micron (8F²)
Elpida
Nanya
Nomenclature
“95nm”
“0.11-micron”
“0.11-micron”
“0.10-micron”
“0.11-micron”
“0.14-micron”
“0.14-micron”
Die Area (mm²)
57.65
78.36
81.00
90.37
93.73
125.45
136.19
Minimum Pitch
0.19
0.23
0.22
0.22
0.23
0.29
0.28
Cell Area (μm²)
0.054
0.079
0.097
0.101
0.105
0.17
0.16
Source: Micron Hong Kong 2004 Analyst Meeting, May 2004. Compiled by DigiTimes.
The relative nomenclatures are shown in Table 1 above. In general, companies halve the minimum pitch and round up or down. Micron’s new 6F² die on a 0.19-micron pitch – the company’s “95nm” node – is shown on the left. Currently, most new Micron DRAM products are rolling out as 6F² designs with a majority of Micron’s worldwide memory volume manufactured on this technology. Micron is also running silicon on its 95nm process node in the manufacturing line.
The bottom row in the table shows how the cell areas stack up; the large differential between Micron’s 6F² technology and the other solutions is clear. Since the DRAM market is ruled by the cost per bit, driving smaller die sizes is always desirable.
Micron’s new 6F² technology
Illustration 1: Traditional 8F² DRAM cell structure and Micron’s new 6F² structure
Note: Highlighted boxes are the size of a single feature
DRAM arrays have historically been built with the repeating unit – a bit that includes a transistor, a capacitor plus half the contact used to access the device – occupying eight feature sizes squared in terms of plain view area. Micron has introduced its 6F² technology over the last 12-18 months. With a given lithography capability, this technology puts the repeating bit in three-quarters of the space used by the traditional 8F² arrangement. Three-quarters is the pure shrink in the array only since there is a little bit of additional overhead associated with the accessing circuitry and periphery. Micron expects that the net over time, on various products, will work out at just over 20% more die per wafer.
Mark Durcan, Micron’s CTO and vice president of R&D, thinks that Micron’s new 6F² technology is the most fundamental change in DRAM architecture in the last couple of decades. Development of the new technology took six or seven years and was a stealth program for most of that time. The product Micron is introducing is claimed to be a third-generation product. Long-term, the company expects the competition will modify their technology roadmaps in order to remain competitive, and some players using process technologies that cannot enable 6F² may be forced to change their schemes.
The 6F² technology was enabled among other things by the availability of new materials that provide low-resistance word lines, storage nodes and reference plates for the capacitors. These new materials are metals that are much more difficult to use in trench structures, presenting an additional barrier to some of the competition.
Illustration 1 also shows many squiggles and wiggles on the 8F² layout, with a lot more straight lines on the 6F². This is what Micron calls a “lithography-friendly” design, and it enables the company to shrink lithography more aggressively than the competition in terms of actual feature size.
At a given technology node, does a trench cell require more capacitance than a stack cell?
Durcan, who has experience with both stack and trench technologies, believes that trench cells require significantly more capacitance at a given technology node than stack cells, and the fundamental reason for this revolves around a phenomenon called variable retention time (VRT) bits.
Memory has a certain cell capacitance and a certain digit capacitance, and the ratio of the two generates a signal on the bit line – it is this signal that differentiates between a 1 and a 0 (on or off). Trench cells tend to have a slightly lower digit capacitance, which suggests that they should be able to get away with a lower cell capacitance, but the opposite is true, according to Durcan.
Before selling a part, cells are written to and tested to ensure the bits are good. However, when the part is packaged, assembled or mounted on a PCB, the thermal cycle the part undergoes changes the retention characteristics of some of the bits – some get better, but some get worse. Because of this, additional margin is included in the product to allow for this change in the retention characteristics – this is the VRT phenomenon, and it is becoming more critical in DRAM for two reasons:
- People want longer and longer refresh times for mobile applications, where power is the preeminent consideration.
- As DRAM is scaled, more and more tightly packed structures and steeply graded junctions are introduced into the substrate, and associated with those are interfaces and stresses on the interfaces that are the root cause of the variable retention times.
In a trench cell, there is a lot more stress management going on in the substrate because of the huge, high-aspect-ratio trenches going way down into the substrate, with other devices immediately adjacent and one of the nodes actually on the trench side wall. Trench cells have historically had higher capacitance per node to account for this variable retention time phenomenon, and this will be one of the reasons why they have more trouble scaling to 0.11-micron and below, according to Durcan.
If trench did not need more capacitance, if it could get away with the same amount – which technology has the advantage going forward as processes continue to scale to smaller geometries? Trench capacitors can only use the inside of the storage node, whereas in stack technology both the inside and outside of structures can be used. Between nodes, the trench aspect ratios are getting worse faster than those for stack structures, said Durcan. Trench may also be more constrained in its ability to implement high-K dielectric materials and metal electrodes inside a trench storage node.
Durcan said, “I think the jury is still out on this or at least on how effectively they can do it. The trench guys would claim they have proved that they can use a high-K gate dielectric and that they can pass the thermal processing required to activate the junctions in the transistors, but the reality is that you haven’t proven anything until you have it in an actual production environment and volume. The stack guys have done this – both Micron and Samsung have implemented high-K dielectrics at the 0.11-micron node, and Micron has also proven this at the 95nm node.”
Increasing capacitor surface area
Another key element in the trench roadmaps is the ability to texture a capacitor inside the trench. This is something that stack cells have done historically and can continue to do. Doing this in the lab is one thing, but actually reproducing this in manufacturing is very difficult and particularly difficult given the types of aspect ratios and minimum critical dimensions that trench technology has.
Illustration 2: Texturing a trench cell. Visualization by DigiTimes, Sep. 2004.
By way of illustration, consider that in a trench structure being produced at the 90nm node with an 8F² cell, the capacitor structure is roughly 3F by 1F in size – about 90nm across. If this is “coke-bottled,” the narrow dimension may be up to 110nm across. In order to get any area enhancement by texturing, when the dielectric is roughly 100Å (10nm), bumps of roughly the same size need to be created within the 110nm structure. Doing that on both sides of the structure means there is (100Å [dielectric] + 100Å [bump]) x 2 = 400Å on both sides, which leaves only 70nm or so between the bumps in the best-case scenario. A top electrode must now be inserted all the way down the high-aspect-ratio structure, and this is nominally around the size of the gap – this is a real technology challenge. The challenge is increased by other technical hurdles, including how the distribution of such small bumps is controlled and how they can be spaced far enough apart so that the dielectric is not plugged.
The issues do not stop there. With post-bump and dielectric deposition for the storage node in the middle of the trench being of the order of 60-70nm across, the distributed series resistance down the center of the trench is a huge issue, which raises the next major trench problem. Traditionally, doped and activated polysilicon has been used in trenches as the storage node. The series resistance of this storage node from the access device at the top of the trench to the bottom is a serious inhibitor to being able to write a good 1 to the cell even if you have sufficient access to the cell. Apart from moving to high-K gate dielectrics for the capacitance issue, Durcan believes the trench manufacturers need to look at metal electrodes inside the trench to address this series resistance issue. This raises the question of whether or not a metal electrode – TiN – can be put inside the trench and device junctions subsequently activated, while avoiding material problems associated with the metal electrode.
This is the first section of a two-part interview. The second section will follow tomorrow.
Marc Durcan, Micron CTO and VP of R&D. Source: Micron, May 2004.
Note: The above article has been compiled from comments made by Mark Durcan, Micron’s CTO and VP of R&D, in an interview with DigiTimes held in the second week of May and supplemented by information given by him during the company’s 2004 analyst conference in Hong Kong.
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