Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: TGPTNDR who wrote (133721)	9/24/2004 7:19:08 AM
From: combjelly	Respond to of 275872

"but is there such a thing as 'static leakage' in cache?" Cache is 6 transistor SRAM, it doesn't need a clock. Now true, there are synchronous elements that need a clock, but that is a minor percentage of the overall circuit. And yeah, Hector is doing his best to maximize revenue. But the cost of materials is a very low percentage of their overall costs so that there are few economic disencentives to running a 90nm process that doesn't quite yield or bin what it should over a 130nm that does as long as the number of good die and binsplits are close. There is one huge advantage to running the 90nm process more. And that is the more wafers run, the more that is known about the process and the more it can be improved. And that leads to the reason to introduce mobiles first. It's ok for mobile chips, especially lower power ones, to be introduced at a lower clock rate. I imagine a 1.4 GHz desktop chip isn't worth trying to sell, minimum seems to be 1.8 GHz. But a 1.4GHz chip running on 35 watts is. That extra 400 MHz, assuming the lower voltage isn't a big factor, could mean a bunch of chips if the bin splits are skewed towards the low end of usable bin splits. At 130nm, dropping the voltage didn't affect the clock rate much until they got close under 1.2 volts, likely 90nm has similar characteristics. So the introduction of the mobile chips first might be due to the fact that they just get more usable bin splits that way. In that context, cache disabled Winchesters fall in the same category. As the process matures, they get faster chips in more than the 10-15k per quarter that FX represents. So I think this might actually be good news. They seem to be doing things in such a way as to maximize the number of chips they can sell. It might indicate that there are certain issues to resolve before they can push up the clock rate. Given the relative competition from Intel, that isn't a problem for the moment. 90nm can supply everything but the absolute fastest chips, which have a pretty low fraction of the overall wafer starts. The net effect is more chips per wafer, and that is good.