FSA panel debates crosstalk doom
By Ron Wilson
EE Times
10/05/2004, 10:49 AM ET
SANTA CLARA, Calif. — Panelists at a workshop here debated the pressing issue of whether crosstalk is killing the semiconductor industry. They found no simple solutions to the problem.
A panel at the Fabless Semiconductor Association Design Modeling Workshop here Monday (Oct. 4) tackled issues ranging from crosstalk analysis tools to how those tools can adapt to process issues.
Tak Young, senior principal product specialist at Nassda, chaired the panel. "Many chips have failed due to crosstalk issues," Young warned, asking whether analysis could get by at the gate level, or was transistor-level crosstalk analysis necessary. Further, he asked if there was a way to avoid the vast number of false positive results often returned by analysis tools.
Maad Al-Dabagh, director of design integrity at LSI Logic, said transistor-level analysis was not an option. "It's just too slow," he said. "We have to use gate-level analysis. But gate-level produces large numbers of errors, so then we have to screen the results. There are several screening techniques, and they all appear to be OK. But what we will need for 90 nm is a statistical analysis of failures so we can calibrate the screening algorithms?"
Henry Jyu, Nassda's R&D manager, added: "Why are there so many different results? We have reports from customers of getting a factor of three difference in delay figures from different tools on the same circuit."
"The difference is in the models," he said. "They range from the very simple aggressor/victim models to circuit simulations that take into account timing windows. Timing is vital: a 1 to 2 per cent difference in timing can make the difference between a circuit being flagged or not flagged for crosstalk. It would be most useful if we had a statistical timing tool integrated into the signal integrity flow."
Jim McCanny, group marketing director at Cadence Design System, disagreed. "There are areas where gate-level models are insufficient. You need a combination of cell-level and transistor-level analyses, and a tool that is smart enough to know when to use each technique.
Wolfgang Roethig, responsible for EDA R&D at NEC Electronics America, responded, "The evidence for that assertion is entirely anecdotal. In fact, you can find transistors in their linear region in any phase of crosstalk. Gate-level analysis is simply not accurate enough."
Bill Mullen, group director of R&D at Synopsys Inc., said Liberty models supported by Synopsys had proved sufficient at the gate level. But Roethig replied that extra effort was required to make the Liberty models work, including characterization of drivers. Mullen admitted that Synopsys was planning to add current-source models to Liberty this year. Unappeased, Roethig pointed out that short-channel transistors, in particular, looked like neither a classical voltage nor a current source, but rather like a source with a nonlinear resistor.
Young asked how to get enough performance out of the tools to do a full-chip analysis. Anticipating that someone would cite "use hierarchical design," Young further asked how hierarchical analysis was possible when, for instance, global nets could disrupt the crosstalk analysis already performed on individual blocks.
Mullen of Synopsys said integration of crosstalk analysis with other tools, especially static timing, was essential to avoid iterations. Filtering at the gate level, and using reduced-order models for interconnect structures are also vital to placing the full-chip analysis within reach of ordinary server farms, he said.
But Mullen was less sanguine about hierarchical design. "Crosstalk does make hierarchical design much more difficult," he admitted. "Overblock routing can invalidate analysis done previously on the block. And interactions between blocks at the boundary can cause problems."
Several panelists offered ways to preserve the hierarchy by adding information to the interconnect-level model of each block. Tao Lin, manager of product development at Magma's signal integrity group, called his approach a "glass box" model. Along with the pin descriptions and external function/timing information, the block model includes a view into the portion of the physical design that lies just inside the block boundary. In order to make the analysis tractable, Lin proposed a shield over critical blocks and to buffer low-order blocks.
Roethig said NEC has been performing full-chip crosstalk analysis since the 180-nm node and had not found computing time a problem, especially with the emergence of cheap 64-bit Linux machines. NEC's approach to hierarchy was to divide the design not into arbitrary blocks, but along natural physical boundaries. "Then when doing global analysis, we only have to mind the boundaries," he said. "Those we can deal with by buffering and providing a track or two of space between the blocks."
Several panelists said avoidance was necessary, but not sufficient. Cadence's McCanny showed empirical data about the relationship between the avoidance and repair techniques. "If you go into crosstalk analysis with less than 500 total violations, you can probably repair the chip," he said. "If you have more than 500, at the very least you will lose control of your schedule. And there's a real possibility that the design is unrepairable. So there is a very real need to avoid violations during the design phase."
LSI's Al-Dabagh urged panelists to "remember that you only need enough accuracy to meet your performance goals. Unless you are designing the next Pentium, you can stop when you are sure the delays are short enough."
Young queried the panel on the impact that advanced process issues such as dummy metal, poly fill and process variations would have on crosstalk analysis.
Al-Dabagh said variations were vital. "Metal and inter-metal dielectric thicknesses have a first-order impact on crosstalk," he said. "We have to understand how they are controlled."
Lin said his data showed that the impact of active fill materials on capacitive coupling was not great. But floating fills such as dummy metal were an issue and had to be accounted for in models.
Roethig warned that at and below 90 nm, parasitics would depend not just on intended features but on context. "For instance, if you actually measure a wire section, it's not a rectangle any more. At best, it's a trapezoid," he said.
Roethig also warned, "Everything is connected. Crosstalk is just a part of a larger picture in which there are many analyses." |
