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Technology Stocks : Applied Materials No-Politics Thread (AMAT) -- Ignore unavailable to you. Want to Upgrade?

To: etchmeister who wrote (12233)	11/29/2004 10:19:20 PM
From: Proud_Infidel	Respond to of 25522

etch, You make apposite points, believe me. I agree with you. Brian

To: etchmeister who wrote (12233)	11/30/2004 11:35:54 AM
From: Proud_Infidel	Respond to of 25522

Benefits stack up for 3-D circuits By Yoshiko Hara EE Times 11/29/2004, 9:00 AM ET TOKYO — Seeking to break the limitations of producing complex ICs on present processes, a startup here plans to stack chips atop one another to create 3-D circuits with advantages it claims systems-on-chip and systems-in-package can't match. ZyCube Co. Ltd. intends to commence fabrication of 3-D chips in the second half of 2005, with commercial devices expected in 2007. ZyCube's 3-D circuits will avoid the extensive internal wiring, propagation delays and power consumption of complex systems-on-chip that integrate multiple functional blocks, the company said. ZyCube will also be able to combine silicon and compound-semiconductor dice into single devices, creating 3-D circuits that cannot be made as single-chip SoCs with present technology. "We've developed a method to build brand-new LSIs," said professor Mitsumasa Koyanagi, a Tohoku University researcher who now is ZyCube's chief technology officer. "It's an ultimate form of LSI fabrication." ZyCube said that its 3-D circuits will also improve upon system-in-package devices, which stack LSIs and connect them via wire bonding. ZyCube will create its circuits with a technology called Smart-Stack, which uses buried vertical vias to improve the number of connections between chips, allowing for parallel operations to improve performance. The company said its approach will shrink fabrication times and lower production costs. Koyanagi and president Manabu Bonkohara were the main forces behind ZyCube's founding in March 2002. Bonkohara at the time was project leader of 3-D LSIs at the Association of Super-Advanced Electronics Technologies, a national R&D institute, having overseen the ASET 3-D research effort that ended in March of this year. "ZyCube is not an extension of the ASET project; I wanted to do business in a much more advanced area of 3-D LSIs than what was done at ASET," Bonkohara said. "Thus I founded a venture company. This is a real venture company, supported by people who understand the technology and have deep pockets." He officially became president of ZyCube in March. Koyanagi has been studying 3-D LSIs since the 1980s and is the developer of a wafer-to-wafer stacking technology, dubbed the Tohoku University Method, that has been widely used as a basis for 3-D development at ASET as well as at overseas companies and universities. The Smart-Stack approach, completed last summer, represents an evolution of the Tohoku method. Devices based on the Smart-Stack technology employ known-good dice or wafers. Any chips or compound semiconductors, including processors, memories, sensors, analog ICs and RF chips, can be stacked and are electrically connected by vertically buried interconnections. Stacked LSIs are already used in system-in-package configurations, but in SiPs the LSIs are wire-bonded. ZyCube says its buried-via approach has an edge over conventional SoCs and SiPs in fabrication time, number of connections available for parallel operation and thinness (as thin as several tens of nanometers). The Smart-Stack technology features long (about 50-micron) and narrow (down to 1-micron) trenches formed in chips or wafers to be stacked and insulated with SiO2. Wiring materials (usually polysilicon) are then used to fill in the trenches so that the trenches function as buried vias. The Smart-Stack technology can be used with known-good dice of different die sizes and semiconducting materials, including compound semiconductors. That opens the door to new functions that cannot be integrated into one chip with present technology, ZyCube claims. "With many buried interconnections, the LSIs are connected by a bus of vast width and operate in parallel," said Koyanagi. "With parallel operation, 3-D LSIs can realize high performance at a low clock frequency. "It's like the human brain. In the brain, neurons operate slowly but in parallel, thus bringing marvelous performance. Three-D LSIs target that direction." In general, the power consumption of ZyCube's 3-D LSI would be about one-fourth that of a conventional device with corresponding performance, said Bonkohara. Smart-Stack configurations tuned for power savings would come in at one-tenth to one-twentieth the power consumption of conventional equivalents, he said. Process details The supporting substrate used for Smart-Stack configurations is a conventional wafer with LSIs fabricated on it. Known-good dice with buried interconnections formed in advance are glued to a quartz glass handling plate. The dice are placed facedown on the substrate wafer and are connected with metal microbumps. An adhesive material that functions as an insulator is injected into the gaps around the microbumps between the supporting wafer and the known-good dice. The handling plate is removed after the dice are bonded to the supporting wafer. The glued dice are thinned from the backside by mechanical grinding and the CMP to expose the bottom of the buried interconnections. A metal microbump is formed at the end of each exposed via. The next layer of known-good dice is aligned for interconnection to the metal microbumps of the first layer, and the same sequence of steps to expose the buried interconnect and then stack the next layer is repeated. The same process is applicable to entire wafers. Koyanagi has made and verified a 3-D LSI that has 10 stacked memory chips, each of which is 20 microns thick. ZyCube was founded with capitalization of 160 million yen (about $1.5 million). This year, the company increased its capital to about $3.2 million to begin full-fledged preparations for 3-D LSI production. "All funding came from angel investors, not from venture capital firms," Bonkohara said. ZyCube's business model is "semifabless" in that only the processes involving the 3-D LSIs are assigned in-house. Chip fabrication and assembly are contracted out. The company has started installing production equipment for a 200-mm wafer line at its Sendai Center, close to Tohoku University. It intends to use this first line for R&D and test production; a separate line will be established for volume production. The company estimates the two lines will require a collective $49 million in new funding. The first commercial devices expected to be produced in the Smart-Stack technology are sensors. A two-stack device is expected in 2007 and a three-stack implementation in 2008. Koyanagi has already developed a working sample of an artificial iris that uses a two-layer LSI stack.