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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: DRBES who wrote (147772)	1/13/2005 5:20:46 PM
From: neolib	Respond to of 275872

An interesting EE Times article comparing Intel and TI's 90 nm processes. eetimes.com Key points Intel achieves 40% higher transistor output current than TI (1.4mA/micron on n-channel width vs. 1.0mA for TI) TI achieves 34X (n-channel) and 21X (p-channel) higher ratios of on/off drive/leakage current than Intel does. Intel SRAM size: 0.9um x 1.28um = 1.15um2 TI SRAM size: 0.65um x 1.50um = 0.975um (Smallest of all 90nm designs the authors have evaluated) Intels estimated cost/wafer 12% lower than TI's Intels process likely to be very critical for mask alignment. This is a very interesting observation. They claim that based on hundreds of SEM and TEM images of "not even slight layer misalignments were found". From this they infer that even slight mask misalignments result in chips which fail testing. They thus conclude that cost + yields results in an overall TI cost advantage at 90nm. Intel uses strain, TI uses 45 degree lattice orientation to increase mobility. TI may have some issues with singulating dice as a result of preferred fracture direction. I thought dice where diamond cut, not fractured. Maybe the cut still can induce fractures which would follow the preferred plane? Wish the article had compared AMD & Intel. Note that TI's process is optimised for mobile, Intel's for speed.