Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: dougSF30 who wrote (148564)	1/21/2005 9:14:28 AM
From: kpf	Read Replies (1) \| Respond to of 275872

doug Can you explain this in further detail? (Did you mean 2MB, also?) Yes. I see where you struggle. I am talking process. See below. AFAIR, Smithfield = 2 x 1MB Prescott Yes. , with the two Prescott dies adjacent on the wafer, with a little bit of connection between the two. And if one part is bad, it may be salvaged as a 5xx (not 6xx) single core Prescott. There are many possibilities to kill a cat. The one you mentioned is what Nathan Brookwood told the world is the speculation of one of his technical consultants. I leave it to your assessment of how probable it is Intel opted for this after you digested the rest of this post - [and consequently the excellence of this industry's perceived experts] Are you simply saying that Smithfield should yield strictly worse than low-speed (2.8, 3.0, 3.2) 6xx parts, having the same amount of L2, but needing an extra core to function? I agree, if so. You lost me with this. Maybe i should just outline some of the relevant underlying semiconductor principles: As usual in this industry, the design for manufaturability is a joint production model, in this case yielding Xeon 2MB, 6xx2MB, 5xx1MB, future Celerons512KB, current Celerons256KB and Sheltons without Level2 Cache in the Cache dimension. Second dimension of yield is binsplits, another one is powerdraw. (There is many more, i am only refering to the relevant ones to explain the principle) Every of these dimension has a distribution which can be predicted fairly well if you know the design parameters in terms of recundancy mechanism for the GDPW-part and cache, for the other dimensions predictions are as good as you know your process parameters. After having 90nm in volume production for a year now, Intel should have all it takes for a good prediction of everything. (while i believe they were a bit off for their first Prescott-approach. As I said earlier, the latter is basically the main reason Intel is deploying the process we talk about anyway.) Now we need to look closer at the powerdraw dimension. The distribution curve here is logarithmic for leakage. Scatterplots of outputs usually show many parts drawing in the 10A range of leakage and a few drawing only in the 1A range. AMD uses these for mobile chips, Intel will make use of these characteristics in a twin package. (This is the reason thermal envelope can be met.) Now for the specs it gets multidimensional. Because this is only one dimension and you got to look at the other two as well, Intel decided to specify Smithfield for 1MB caches because there is not enough fullcache parts meeting the powerdraw required for the predicted volume. Same applies for Clockspeed. Hth. K.