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To: dougSF30 who wrote (148566)1/20/2005 11:15:18 PM
From: PetzRead Replies (1) | Respond to of 275872
 
Doug, % good die per wafer is a meaningless statistic anyway. The fact is, xbitlabs estimated that each Smithfield will be 2.1x as big as a Prescott. With the increased die size, Intel will be lucky to get 40% sa many Smithfields as Prescotts from a single wafer.

Second, bin-split yields of Smithfield will be as bad as the top 3 speed grades of Prescott -- 3.4, 3.6, 3.8. I define "bin-split yield" as the percentage of working chips that can be sold at the desired speed. So any Smithfield that only hits 2.6 GHz isn't sellable.

Heres the key point: 3/4 of Prescott hit 3 GHz now, but very few Prescott can hit 3 GHz at the lower Vcc necessary to meet the power spec! A 2.8 GHz dual core part has to hit 2.8 GHz at a LOWER VOLTAGE, or it can't be sold as a 2.8 GHz Smithfield. Lower voltage is the only way Intel can meet 130w TDP. According to tomshardware guide, a 3 GHz Prescott dissipates 85 watts at running Prime95, arguably not the worst case software. No way can they get that down to 65 watts without a lower Vcc. Only a few Prescotts can hit 3.6 or 3.8 GHz, and they can only do it with a BOOST in Vcc. (Iccmax takes a +50% jump between 3.4 and 3.6 GHz, so I suspect the Vid pins are programmed for an extra 0.15v or so.) My contention is that if you drop the Vcc significantly (0.1 to 0.2v) below the nominal value for 3 GHz, very few Prescotts will still be able to run at 3 GHz. So the 75% binsplits at 3 GHz might turn into 25%. That, coupled with 40% as many good die to begin with, is a disaster.

Petz