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To: Petz who wrote (148722)1/24/2005 12:02:05 AM
From: etchmeisterRead Replies (1) | Respond to of 275872
 
most of the GDPW reduction is due to defect density

Hi Petz
but defect density should remain constant;
on an absolute base there should not be more defects (because the wafer doesn't care whether it's SC or DC).
However a "hit" is becoming more significant on DC because you "kill" two dies:
there seem to be 3 factors :

1.) increase of die size by x % due doubling core; that's fairly straight forward assuming one has mm2 for the new DC (benchmark - I assume - would be 90nm Prescott)
2.) increasing die size versus yield (DD should remain constant; however killing one DC die is worse because the DC die is larger compared to SC; however from processing point of view there should be no difference or IOW DC should NOT increase DD)
3.) increasing die size leads to more silicon real estate loss at the edge of the wafer

So IMHO everything should boil down to die size and both INTC and AMD (at different degree) should be impacted when moving from SC to DC.