Hi Bruno,
This is a somewhat dated and do not know how far they have progressed so far. 2004 has come and gone and obviously they are running behind.
-Pam
David Lammers David Lammers
EE Times
(08/02/2002 5:04 PM EDT)
AUSTIN, Texas — Putting their legal differences behind them, Advanced Micro Devices, Fujitsu and Saifun Semiconductors are combining resources in a push to introduce 4-bit-per-cell flash technology by 2004.
The partnership was announced last week, shortly after the trio agreed to the comprehensive settlement of a lawsuit that Saifun, claiming patent infringement, had filed against AMD and Fujitsu in a New York federal court last February. The settlement calls for AMD and Fujitsu to invest in Saifun and collaborate on product development, with the 4-bit/cell technology as a primary target. Quoting unnamed sources, an Israeli newspaper last week put AMD's stake at $50 million, but Kevin Plouse, vice president of technical marketing and business development at AMD's flash unit, said he could not confirm a specific dollar figure.
If successful, the 4-bit effort could give Intel Corp. a run for its money in the nascent market for high-density data-storage flash devices for third-generation wireless phones, analysts said. Reportedly, "the Saifun die size is really small," said Alan Nogee, senior analyst for wireless-component technology at In-Stat. "When you combine that with AMD's and Fujitsu's ability to promote and manufacture flash worldwide, it is a good mix."
Intel pioneered 2-bit/cell flash technology with its StrataFlash line, introduced in 1997. StrataFlash uses four levels of charge to create 2 bits per cell. But scaling to 4 bits/cell would require 16 different levels of charge, a difficult challenge.
AMD and Fujitsu are currently rolling out a 2-bit/cell flash called MirrorBit, starting at the 64-Mbit density. The MirrorBit approach traps two pockets of electrons in a nitride layer under a bidirectional gate. Saifun, based in Netanya, Israel, uses a similar approach in its NROM technology.
Simple as two plus two
The MirrorBit and NROM devices store two physical bits, thus the "multibit" moniker, while StrataFlash is a "multilevel" cell technology. To get to 4 bits/cell, AMD, Fujitsu and Saifun plan to combine multilevel and multibit technologies, putting four levels of charge in each of the two physical bit locations within the cell.
AMD's Plouse said the Saifun lawsuit caused concern among shareholders that the MirrorBit rollout would become entangled in a drawn-out courtroom battle. "What got our attention is when Saifun dropped a lawsuit on our desk. We looked at what they were doing and were very impressed, so we decided to collaborate with them," Plouse said.
He denied, however, that AMD had based its MirrorBit approach on Saifun's technology. AMD and Saifun engineers engaged in six months of discussion in the late 1990s, Plouse said, but AMD decided against the Saifun approach in several key areas and went on to develop the MirrorBit technology independently. "We did talk and did an assessment of the Saifun technology over six months, but came away away with the conclusion that it was not going to work," Plouse said.
Saifun apparently thought differently, and filed suit. In a phone interview last week, chief operating officer Kobi Rozengarten called the settlement and partnership with AMD and Fujitsu a "win-win" for all sides. He declined to discuss the lawsuit, saying, "We want to talk about the future, not about the past."
The MirrorBit approach moves away from the unidirectional conduction used in floating-gate flash to a bidirectional gate. A nitride layer under the gate can trap charge on either side of the cell. A bit is read in the opposite direction from a bit being programmed, Plouse said.
AMD is currently shipping 64-Mbit MirrorBit parts with 2 bits per cell, and over the next two quarters plans to ship 128- and 256-Mbit designs. When AMD's 0.13-micron flash process is ready at Fab 25 here next year, and at jointly owned AMD-Fujitsu fabs in Japan, AMD and Fujitsu plan to bring 512-Mbit MirrorBit parts to market, Plouse said. The two are converting all their high-density flash product lines to the MirrorBit approach, a challenge to Intel, which currently dominates the high-density market. The rivalry may intensify if the pair can produce 4-bit/cell devices reliably.
Saifun has 4-bit/cell prototypes working in its laboratory, well ahead of AMD's research effort. Plouse said the collaboration with Saifun will speed up AMD's 4-bit/cell introduction by at least six months.
Saifun also brings a significant cell size advantage to the new partnership. Richard Gordon, memory analyst at Gartner Dataquest, said Saifun's 2-bit/cell NROM uses a novel approach to buried contacts, allowing closely spaced bit lines. Saifun engineers have figured out ways to implant arsenic in the bit lines, and to use tungsten-silicone and polysilicon for the word lines. The result is a cell size appreciably smaller than AMD's MirrorBit and much smaller than the conventional floating-gate flash technology. "Our approach is three times smaller than our competitors'," Rozengarten said.
Plouse said AMD can now build a memory cell 3.5 times larger than the lithographic feature size, expressed as F. By pushing the oxide growth, optimizing the implants and other process improvements, Saifun has managed to create prototype cells that are 2.5 times F, he said.
Analysts said multibit flash technologies at some point may compete with magnetoresistive and ferroelectric RAM, Ovonic memories and polymer-based devices. Alan Niebel, a flash analyst at Webfeet Research (San Diego), said he believes it will be 2005 or 2006 before Intel can ready its Ovonic technology, which uses a chalcogenic, compound-ceramic material.
Because StrataFlash will be difficult to scale technically, Niebel said, "AMD may be in a better position than Intel," since the NROM and MirrorBit approaches have simpler mask structures and 30 percent smaller die sizes than the comparable StrataFlash devices.
MirrorBit also may be able to compete on cost with NAND-type serial flash architectures while preserving the attributes of a NOR-type flash, including faster first-access and read times. But the NAND flash vendors are not sitting idle. Toshiba and Samsung Electronics have shown gigabit-density NAND prototypes — Toshiba's supports a throughput of 20 Mbytes/second for reading data. Hitachi recently gave details of its impending introduction of a 2-bit/cell architecture, Assisted Gate-AND, with a sustained write speed of 10 Mbytes/s, three times faster than today's NAND parts.
Cell phone target
Plouse said he believes the big market for the 4-bit/cell MirrorBit will be in cell phones. Matsushita has introduced a 3G phone in Japan that supports external flash cards, which usually rely on NAND-type flash devices.
However, Plouse said 3G service providers may frown on the use of flash cards. "They want people to use their cellular networks to transmit data. They don't want people going with a card from the phone to a computer with a DSL connection," he said. "This is a massive market developing for wireless data that will account for more than 40 percent of flash bits when 3G phones become established."
AMD estimates that by 2006, wireless data storage will account for roughly 40 percent of flash bits shipped. High-density on-board storage of e-mail, calendars and contacts; "rich media" such as music, photos and video; and wireless game playing, navigation systems and map storage all will result in a boom for high-density flash devices, in the company's view.
Several analysts were more conservative about the prospects in 3G phones. Still unclear, they said, is whether the phones will store photos, music, and data largely in external flash cards or in on-board memory.
Brian Matas, an analyst at IC Insights (Phoenix), pointed out that many people in Europe and Asia spend time each day on trains, where a 3G phone can be a means of fending off boredom during long commutes. "I think the built-in flash will be preferable to flash cards. People don't want to take out a flash card — on-board storage means one less thing to fiddle with," said Matas.
View from Intel
"Already we are seeing remarkable increases in density for text messaging and photo capture — all good news for the flash industry," said Troy Winslow, product-marketing manager at Intel's flash division. Phones used in 3G networks often have 128 to 192 Mbits of flash on board, he said, and most use NOR-type devices that are partitioned for both code execution and data storage.
Moving forward from its 5- and 3-volt offerings, late this year Intel expects to introduce a line of 1.8-V StrataFlash devices with densities ranging from 32 to 256 Mbits. Using 0.13-micron process technology, both Intel and AMD have 512-Mbit multibit flash products on their road maps for next year.
Winslow said cell phone customers often shy away from high-density monolithic flash because the package is too large, opting instead for stacked packages. Intel has packages with seven and eight stacked chips in development, he said. "Using stacked 128-Mbit or even 256-Mbit devices, customers get a smaller-footprint package [than with a larger, monolithic die]," he said. "Stacked packages will be able to meet the density requirements for the next couple of years."
Winslow said Intel has work going on in the labs to move StrataFlash to 4 bits/cell, but cautioned that any 4-bit approach will take time. "AMD can talk about their plans, but there is a big difference between prototyping and being able to manufacture a multibit device in volumes," he said.
"It took Intel quite a long time to get a production-worthy design at 2 bits/cell, so it sounds suspicious to me that these companies could announce a plan at this point for a 4-bit/cell product," Winslow said.
Gordon, at Dataquest, said Intel captured 26 percent of the overall flash market last year, up from 22 percent in 2000. AMD held steady at 13 percent, while flash partner Fujitsu gained a point to take 11 percent of the market. STMicroelectronics also gained share, and holds roughly 8 percent of the market.
Advantages in time, money
Gordon said Intel is likely to have a tougher time getting to 4 bits/cell than AMD. Moreover, AMD "may be able to get to a more efficient use of silicon by working with Saifun, which has some very innovative techniques," he said. However, a bigger question is who will be able to supply flash at the lowest cost per bit, Gordon said. "Customers want the lowest bill of materials."
Saifun has 120 employees in Israel and another 60 people working at the Ingentix joint venture with Infineon Technologies, which is using Saifun's technology in memory cards. That effort will continue, even as Saifun transfers its technology to AMD and Fujitsu. "There may some overlap with Ingentix," Plouse said.
Saifun has another joint venture with Fairchild Semiconductor for EEPROM devices, samples of which are now shipping. "We use the same approach for code flash, data flash and EEPROM," said COO Rozengarten.
Rozengarten said company founder Boaz Eitan once worked at Intel's nonvolatile memory operation and later at now-defunct Wafer Scale Integration Inc. Eitan "holds many patents in the nonvolatile-memory field, including multilevel-cell technology," Rozengarten said.
According to information on the company's Web site, the Saifun NROM cell is a charge-trapping memory device in which the gate oxide is replaced with a thin oxide-nitride-oxide multilayer. The intermediate nitride layer is the retaining material for two separate pockets of trapped electrons, close to the bit line junction edge.
Programming is done by channel hot injection of electrons located in the nitride layer. To program the opposite side of the cell, the drain and the source reverse roles during programming. By raising the bit line voltage and leaving the word line at zero or negative voltage, enhanced tunneling occurs by injecting hot holes near the bit line junction, causing holes to enter the nitride and recombine with trapped electrons, the company said. |
