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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Amy J who wrote (180776)	4/14/2005 9:37:58 AM
From: Proud_Infidel	Respond to of 186894

EUVL alpha tools to ship to IMEC, Albany in Q1, says Intel Peter Clarke EE Times (04/14/2005 7:28 AM EDT) MUNICH, Germany — European lithography equipment vendor ASML Holding NV is working on two alpha machines for extreme ultraviolet lithography (EUVL) in parallel, and the company is expected to install one at IMEC vzw (Leuven, Belgium) and the other at the Albany campus in New York State. Paolo Gargini, Intel's director of technology strategy and Intel Fellow, confirmed that Intel would make use of the EUV stepper installed at the IMEC European research organization for research purposes, at least initially. The appropriate time for EUV lithography to be used commercially is widely held to be the 32-nanometer manufacturing process node due to debut around 2009 or 2010. This is where EUV stands on the International Technology Roadmap for Semiconductors (ITRS) of which Gargini is chairman. "The number one choice for 2010 was EUV," said Gargini at a press meeting here implying that EUV would not only be successfully introduced but would eclipse the immersion lithography that is now looking necessary for manufacturing at the 45-nm manufacturing node. "Lithography must break through to the shorter wavelength of13.5 nanometer," he said. "Activity on our side started in 1996. But we also take part in research elsewhere." Gargini said there are two EUV alpha tools nearing completion that would be shipped in the first quarter of 2006. One would go to IMEC and the other to Albany, Gargini said. "In the first quarter the first fully integrated EUV lithography machine will be delivered to IMEC at Leuven. And as we are members [of industrial affiliation programs] we'll make use of it." ASML is the key to that industrial affiliation program on lithography. In addition ASML, working in collaboration with IBM Corp. and New York State, announced plans to invest $400 million, in a research center at the University of Albany, ASML's first outside of Europe, in Jan. 2005. Peter Kuerz, senior EUV systems manager for Carl Zeiss SMT AG, confirmed that his company is working on the lenses for two EUV alpha tools under construction. Intel also has its own micro-exposure tool, delivered to Intel in October and which looks like a small submarine, Gargini said, and activity in EUV had shown progress in certain key areas, he said. "In the last six months we've seen reports of a 40-watt optical source. We believe we will be able to get in to the 100-watt regime, needed for commercial wafer throughput," Gargini said. Gargini also showed data with EUV blank masks with the number of defects reduced to optical lithography levels. "The EUV masks are done in Santa Clara and then sent to Oregon, where the submarine is." In 2009 we expect a production machine at 80 to 100 wafers per hour to be available. Intel joined a major IMEC industrial affiliation program on advanced lithography as a core partner in October 2003.

To: Amy J who wrote (180776)	4/14/2005 11:00:26 AM
From: Proud_Infidel	Respond to of 186894

Intel may drop high-k gate dielectric, despite work on next version Peter Clarke EE Times (04/14/2005 10:39 AM EDT) MUNICH, Germany — Intel Corp. may drop the use of a high-k dielectric in the transistor gate stack at the 45-nanometer manufacturing process node, despite the fact that the company has got what it believes would be a suitable dielectric and gate combination, according to Paolo Gargini, Intel Fellow and the company's director of technology strategy. Gargini, added that the company is working on a second high-k material, with a yet higher dielectric constant, but emphasized that the company's process technologies beyond the 65-nm node are not fixed. He said engineers were being encouraged to find a different engineering solution to the use of high-k. All the leading chip makers have conducted research looking for replacements for the industry's workhorse gate insulator, silicon dioxide, which it was thought would be unsuitable for transistors at 45-nm manufacturing process node and finer geometries, due to excessive gate leakage currents. Intel itself announced that it had identified a high-k insulator and metal-gate materials in the plural suitable for use in Intel's 45-nanometer generation P1266 manufacturing process due for introduction in 2007, in November 2003. The company has resolutely declined to reveal its choice since then. Gargini also declined to identify Intel's high-k material and metal gate or other gate structures. "It's a secret," he said. Other industry players have been more forthcoming, with nickel-silicide gates over hafnium oxynitride mixtures emerging as the material system of choice, albeit one that was beginning to cause flutterings of engineering disquiet at the IEDM conference in December 2004. However, according to Gargini, Intel's high-k solution works well technically allowing the 1.2-nm thick film of silicon dioxide gate insulation, used in Intel's 90-nm and 65-nm process generations, to be replaced with 3.0-nanometers of the new material while achieving a one hundredth of the gate leakage current. "We've got this in our back pocket. If we see a threat we'll introduce it," Gargini said. When challenged that the conventional wisdom was that semiconductor makers had to go to high-k dielectrics and metal-gates, Gargini said: "It's an option for 45-nm. We've told the engineers we'll pay them more if they can avoid putting it into production." Gargini added that the use of high-k dielectrics would involve a minor additional complexity to the manufacturing process and thereby add a few percent to production costs, but that Intel was always looking for pragmatic ways to avoid or delay making such changes. "If we can delay the introduction until 2009 we will. It's not decided yet. One way that Intel was able to continue with silicon dioxide gate insulation material was by understanding how overlayers, such as silicon nitride, and doping could be used to introduce tensile and compressive strain in a transistor's semiconductor channel. Using cross-sectional diagrams Gargini showed how Intel had used germanium to dope sources and drains in the 90-nm p-channel transistor to introduce compressive strain and used a silicon nitride overlayer to introduce tensile strain in 90-nm n-channel transistors. For the 65-nm transistor he showed a single slide and said the silicon straining had been "enhanced for performance and power efficiency" leaving it unclear whether Intel had again used germanium to swell up the source and drain regions. While Intel' apparently has a stable first choice high-k dielectric material with an effective constant three times higher than that of silicon dioxide, the company is already working on developing a second generation material with an effective constant five times higher than that of silicon dioxide, Gargini showed in a slide.