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Technology Stocks : Applied Materials No-Politics Thread (AMAT) -- Ignore unavailable to you. Want to Upgrade?

To: Cary Salsberg who wrote (14461)	4/20/2005 10:19:14 AM
From: Proud_Infidel	Respond to of 25522

Sematech lists top technical challenges for 2006 EE Times (04/19/2005 2:36 PM EDT) SAN JOSE, Calif. — Chip-making consortium Sematech on Tuesday (April 19) listed its "Top Technical Challenges" for 2006. The list indicates that the IC industry still has a long ways to go to solve some new — as well as older — chip-manufacturing technologies, such as advanced gate stacks, 193-nm immersion and EUV lithography, mask infrastructure, and low-k dielectrics. Sematech (Austin, Texas) also placed planar bulk transistor scaling on the list for the first time and for good reason. For example, Intel Corp. said it may drop the use of a high-k dielectric in the transistor gate stack at the 45-nanometer manufacturing process node. This implies that Intel and others are looking to extend silicon dioxide for gate stacks. The Sematech challenges reflect the consensus of the consortium's member companies, and are grouped below by technical area. Lithography Immersion lithography. This technology has been developed as a method for extending the resolution and depth of focus of optical lithography, by interposing a liquid between an exposure tool's projection lens and a wafer. Prototype immersion tools are beginning to arrive in advanced manufacturing fabs. Mask infrastructure. This is critical to improve the capabilities and reduce the overall cost of photomasks for both 193-nm immersion and extreme ultraviolet (EUV) lithography. Resists. The market must determine the practical and theoretical limits of chemically amplified resist platforms on new materials approaches for 193-nm immersion. It must also study the ultimate resolution, line edge roughness (LER) and sensitivity for EUV resists. EUV infrastructure. This includes the development of critical technology components to enable the introduction of extreme ultraviolet lithography into manufacturing later in the decade. Front-end processes Advanced gate stack. This involves the development of high-k dielectrics for logic and memory products, metal gate electrodes, dual metal gate transistor processes, and various electrical characterization methods for metal/high-k devices. Non-classical CMOS. This includes infrastructure development for alternative device technologies, such as strained silicon, silicon-on-insulator (SOI) double-gate metal-oxide semiconductor field-effect transistors (MOSFETs) and multi-gate FETs (MuGFETs). Planar bulk transistor scaling. This covers the development of technologies to enable the continuation of conventional MOSFET scaling for as long as possible. Potential solutions include channel material engineering (GeOI, III-V channel, hybrid silicon); advanced strain engineering; new doping and annealing approaches; and metallic junctions. Low-k dielectrics and process compatibility. Low-k is critical to advanced semiconductor manufacturing because it reduces line-line capacitive coupling and allows metal lines to be packed closer together on a chip, with less risk of electrical signal leakage. Metrology. This is a critical enabler to the achievement of increasing device densities and decreasing feature sizes on advanced semiconductors. Manufacturing effectiveness and productivity. A series of factory- and equipment-related projects aimed at improving both equipment and overall factory productivity, and reducing costs in today's and tomorrow's fabs. These projects include e-manufacturing; advanced equipment and process control; advanced equipment software testing; short cycle time and short ramp-ups; equipment and fab agility; and standards development.