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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: KeithDust2000 who wrote (156685)	4/17/2005 8:42:26 PM
From: Elmer Phud	Read Replies (1) \| Respond to of 275872

Keith I simply can't think of a mechanism by which a chipset could outperform an L3 cache. Reading IBM's documentation, they are saying that a transaction first goes to the L3 then to the chipset. I have been under the impression that the transaction goes to both simultaniously. If a L3 hit occurs or a hit or hitm from another agent then the other transactions are discarded. If I am wrong and the accesses are sequential rather than concurrent then perhaps the X3 approach has greater merit.