Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Elmer Phud who wrote (181279)	5/19/2005 7:37:55 PM
From: Ali Chen	Read Replies (1) \| Respond to of 186894

"Ali addresses a valid point. Intra-die parametric variations." Now you are awaken. Good. "What he doesn't realize is that it is already factored into the yield numbers because wafer sort tests for far more than just functionality." What you don't realize is that I am addressing not simply a "valid point", I hint you to a showstopper for the whole silicon industry. Since your horizon of vision is as wide as a keyhole, let me embark on a trouble to enlighten you on some of it's implications. This effect means that each of your dies have fast/leaky spots and slow spots in different parts of the _same_ die, which means that each chip is likely both thermally limited and speed limited at the same time. Worse, this parametric intra-die variation can hit any functional unit, so the traditional speed-path post-silicon analysis does not work anymore, you can't determine and fix the speed path later because it is now non-deterministic. Because of intra-die variations, various test coupons and ring oscillators are no longer an indicator of the final chip speed. These are kind of "defects" that do not show in full in bare functionality testing at wafer level, but show out only under full-stress tests. That's why you may see "world-class yields" at wafer sort, but don't see even 4GHz processors, and forget about promised 6-10GHz. The good thing is that you likely can reuse many dies as lower voltage and lower frequency "mobile" chips. The next "process generation" will suffer from this effect to even higher degree. "It would just go over his head anyway..." Sounds like you are speaking of yourself, remember your famous "1 million Coppermines per week flood"? Wafer-sort yields were good too... - Ali