SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: Elmer Phud who wrote (181284)5/20/2005 12:28:05 PM
From: Ali Chen  Read Replies (1) | Respond to of 186894
 
ehud, "You are 10 years behind in your thinking. Go look up "transition fault" and "stuck at fault". They are both included, and more in modern wafer sort testing. The magazine you read must be very out of date."

It is your ATM manual that is out of date. Or your old Tetramax program. You stuck in your past and can't comprehend that you can't check for delay faults in every path when the speed path candidate is a non-deterministic moving target due
to 30-40% speed variability in transistors across each die.
There are millions of nets on CPU chip, and any one can become a critical path given this variability. Do you have a test pattern for every path in the chip? How much time it would take to develop such test, debug it, and correlate with output?

"Are you trying to make a case that Intel has to scrap a large number of those good die because they are later found to be too slow to sell due to intra-die parametric variations that can not be screened for at wafer sort?"

Listen, you are not the one who receives daily status upgrade on Intel's yield with improvement analysis details, right? You look at the same "world class yield" pictures from PPT slides as anyone else. People were mentioning to you on several occasions about apparent discrepancy between Intel total capacity and visible chip output. Could it be a natural explanation? Did you learn anything from your "one million Coppermines per week" blunder? Apparently not.

"Do you mean to imply that Intel's sort yields are misleading?"

Why not? Do you know the definition of "world-class yields"
on 90nm? Why do you think that it is the same 97% as on 180nm?
Could it be that there is no "defects" but the speed parametrics is not up to what market needs?

"Do you suggest that other semiconductor manufacturers are immune to the defect types mentioned above?"

What kind of idiot would be so silly to infer this? How someone could possibly be immune to laws of Physics?

"If you have some other point then I'm afraid you're not doing a very good job of presenting it."

What you need to be afraid of that all this stuff seems to be slightly over your head (judging by your "stuck at fault" remark).

Cheers,
- Ali