Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: THE WATSONYOUTH who wrote (159382)	5/20/2005 12:55:03 AM
From: Elmer Phud	Respond to of 275872

Andy Grave - AKA TWY and perhaps several other aliases You've missed the point. Ali was apparently implying that Intel's statement that they have world class yields was misleading because (again apparently) according to the magazine article he read intra-die parametric variability makes reported yields, which are traditionally at the wafer sort level, misleading. Implied in his ill thought out rant was that final yields will be much worse because the parametric variablilty will result in what amounts to delay faults or slow speed paths which in his understanding can't be screened at wafer sort but will cause either failures or a speed limiter later on at final test. Where he got the notion that they can't be screened early on, thus making wafer sort yield misleading, is based on an out of date understanding he has on modern DFT principals and modern test capability. I will also say that your analysis, if it was intended to address the cause of intra-die parametric variability was far off the mark for Intel but could easily be spot on for IBM with all their process problems. Too bad.

To: THE WATSONYOUTH who wrote (159382)	5/21/2005 1:49:43 PM
From: Ali Chen	Respond to of 275872

TWY, "if the mask produces a distribution which meets the ACLV target (say +/-50A 3 sigma for a 90nm process) ... the reduction on exposure is only 4x or 5x....so you are all ready dealing with sub .50u chrome. Think about it." I do realize that quality of masks becomes increasingly important, the price of mask set is now counted in millions $$. However, I am struggling to understand how the mask defect model accounts for random chip-to-chip intra-chip variability. People are saying that two neighbouring transistors can vary in parametrics by 30-40% today, and the variations are unique for each chip. I don't understand how (presumably) static linewidth deviations in the same mask (considering single image per mask) can cause such wide and uncorrelated variations if chemical kinetics is not heavily involved. Regards, - Ali