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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Elmer Phud who wrote (181333)	5/24/2005 3:02:09 AM
From: Ali Chen	Read Replies (1) \| Respond to of 186894

Ehud, "In the past the model used was called the stuck-at model, where potential defects would be modeled as if the defect looked as though a node was stuck at either a 0 or 1. They were considered "hard errors"." Man, you are a piece... Just few posts back, siliconinvestor.com you suggested me to brush up on my knowledge and outlined few "modern" techniques. You said: "Go look up "transition fault" and "stuck at fault". They are both included, and more in modern wafer sort testing." Now you are calling them "in the past". So what was it? LOL! I guess you have a longer way to learn since your use of term "soft error" is completely out of wack - soft errors are random correctable errors, while the intra-die parametric variations are as hard as your old "stuck at fault". You also forgot to tell me how "effective" is the IDDQ technique these days... "they would much prefer catching these sort errors at wafer sort, rather than adding expensive packaging only to throw the part away later." It is a bold misinterpretation, I never said "throw away", I said "re-use". For a wafer with few 90nm Xeons and mobile Pentiums-4, Intel manages to churn out about 20 bins of Celerons, and about 20 bins of overheating regular Pentiums with different broken functional parts. Do you know how many 2.26GHz Celeons were included in those victorious "defect density" slides? You don't. That was my point. - Ali