"More phones are being sold, but profit margins are shrinking,"
Nokia to Implement TI's First Integrated Single-Chip Solution for Mobile Phones
January 24, 2005
Nokia and Texas Instruments today announced the cooperation whereby Nokia will incorporate a single-chip solution based on TI's Digital RF Processor (DRP) technology to its future mobile phones. This cooperation will make Nokia's handsets cheaper, especially in high-volume entry markets.
TI announced its intention to integrate the bulk of handset electronics on a single chip (including digital baseband, SRAM, logic, RF, power management and analog functions) already in 2002. They promiced to sample the first real product in 2004. The first version of the single-chip solution, which sampled in December 2004 and was developed through TI's advanced 90nm CMOS manufacturing technology, targets the mass-market voice-centric marketplace.
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I don't understand why Carl is so downbeat
TI and Intel hightail it into 65 nm
Ron Wilson , David Lammers
EE Times
(03/07/2005 9:00 AM EST)
Austin, Texas — As the majority of the chip industry dips a toe into 90-nanometer production, Intel Corp. and Texas Instruments Inc. are moving to the 65-nm node as fast as they can. "Intel and Texas Instruments appear to be a full node ahead of most of the industry," said Risto Puhakka, president of VLSI Research Inc. (Santa Clara, Calif.).
Texas Instruments last week announced it was delivering "fully functional" samples of a wireless baseband device based on its 65-nm process, with Nokia the presumed customer. Analyst Will Strauss of Forward Concepts (Tempe, Ariz.) said he expects TI to be shipping 65-nm cell phone chip sets late this year and to use the doubled transistor counts of the finer process to bring Bluetooth, PDA, high-resolution camera, GPS and Wi-Fi functionality to a handset.
At the Intel Developer Forum in San Francisco last week (see story, page 8), Intel executives spoke of 65 nm with nearly every breath. The company's dual-core 65-nm Yonah processor is due to ship at the end of the year and as many as six 65-nm MPUs will move into production next year.
Intel traditionally has used each new process node to push megahertz, but that's not entirely the case now, as the chip giant moves to dual-core processors at less-aggressive clock speeds, said Dean McCarron, principal analyst at Mercury Research (Cave Creek, Ariz.). Intel's 90-nm process got close to 4 GHz before Intel killed that product in favor of dual-core designs last year.
"The heart of the 90-nm process was at 3.2 GHz," said McCarron. "The 65-nm process is a shoo-in for 5 GHz, but there are a lot of indications that Intel is moving from a performance focus over to a multicore approach, with multithreading and power-management techniques for both the desktop and server markets."
Advanced Micro Devices Inc. expects to begin 65-nm microprocessor production in 2006 at its Fab 36, now under construction in Dresden, Germany. McCarron said it is not clear when or how quickly AMD will move to 65-nm design rules in volumes. With its use of silicon-on-insulator technology, AMD may be able to wring more speed, at acceptable levels of power consumption, at 90 nm, McCarron said.
Elsewhere, Strauss said he counts Samsung Electronics, the second-ranked handset maker after Nokia, as "a coming force in cell phone chips." By virtue of its DRAM and flash memory production, Samsung is well down the path toward 65-nm line widths, and that could make it a bigger player in this sector, Strauss said. Now, Samsung largely supplies its internal handset division, but its focus could broaden to external customers.
Sony could push IBM Corp. into volume production at 65 nm for the chips used in the Playstation videogame market, said Puhakka of VLSI Research. But for now, TI and Intel are the ones to watch. "Intel may be running more 65-nm wafers now, as it gets ready for volume production, than TSMC [Taiwan Semiconductor Manufacturing Co.] is running at the 90-nm node," he said, adding, "We do expect the integrated device manufacturers, including IBM, Intel and TI, to move to the 65-nm node much faster than foundries" like TSMC.
A spokesman said TSMC created a 65-nm SRAM test wafer at the end of December and has "verified that our 45-nm transistors work in the R&D labs." But as of this quarter, TSMC expects that 90-nm wafers will account for about 3 to 4 percent of its total wafer production. That figure will rise to about 10 percent by the end of the year, as leading customers such as Altera, Broadcom and Qualcomm begin ramping up their 90-nm designs, the spokesman said.
Strauss of Forward Concepts said the 65-nm node provides more chips per wafer, potentially with smaller dice that yield better than 90-nm chips. If done right, 65-nm transistors can reduce both active and leakage power, and deliver higher speeds, he said.
A quick move to 65-nm design rules gives TI a competitive advantage in high-volume applications, said Dennis Buss, a vice president in TI's silicon development group. "Sure, the additional complexity increases the wafer cost by 20 percent," he said, "but the cost per die drops by 40 percent, and that is of obvious importance to any high-volume business."
Buss said the move to 65 nm involves extra work to control power, including keeping interconnects as short as possible. To that end, TI has introduced three power-saving techniques: dynamic voltage scaling, back-biasing of the SRAM memory blocks and retention flip-flops that allow blocks to go into sleep mode without a rewrite of the logic or memory content.
TI will do three spins of its 65-nm process: low voltage (for cell phone ICs), general purpose (for DSPs) and high performance (for the Ultrasparc microprocessor designs of Sun Microsystems Inc.).
To boost the performance of the 65-nm high-end process, Buss said TI is considering two options in addition to the nitride-based strained-silicon techniques it uses at the 90-nm node. TI researchers now are in the final evaluation stages of silicon with a different crystal orientation to boost PMOS performance. At the same time, the R&D organization is increasing strain at the PMOS devices by depositing silicon germanium at the source and drain regions, an approach that Intel pioneered at its 90-nm node. "Using a different crystal orientation involves zero cost adders, while adding silicon germanium does add cost," Buss said in a briefing at the International Solid-State Circuits Conference last month. "But we may get a 10 to 15 percent boost with the oriented silicon, while the additional strain at the source-drain with the deposited SiGe may give us a 25 percent boost. It's a trade-off between cost and performance."
Many technologists believe the 65-nm transition may be relatively straightforward. At the GlobalPress Summit in Monterey, Calif., last week, Mark Pinto, chief technical officer at Applied Materials Inc., said the 65-nm node is largely a refinement of what was learned at 90 nm, with increased use of strain engineering to improve channel mobility. At least initially, it involves no new materials or process steps.
But early adopters of 90-nm CMOS expressed similar optimism. Since the process used essentially the same materials and structures as 130 nm, all the heavy lifting was presumed to have been done. In practice, this proved untrue. It was quickly found that existing circuit design techniques were inadequate to control power dissipation at 90 nm, with its huge transistor counts and unprecedented leakage currents. New techniques, including multiple threshold voltages, voltage islands and dynamic voltage and frequency adjustment, had to be conceived, tested and somehow supported in the tool chain.
Even with all this work, the 90-nm ramp has not been a happy experience. In private, a number of industry executives have said there are very few 90-nm designs actually in production at acceptable yields today. That doesn't mean no wafers are being run, however. "We have about 40 tapeouts so far for our 90-nm process," the TSMC spokesman said, and as of February "we are running about five thousand 300 mm wafers per month on 90 nm."
Still, there's a gap between a carefully crafted design with extremely conservative rules and the kind of designs that are possible for the majority of chip design teams.
Pinto of Applied Materials was more cautious about 45 nm. The introduction of high-k materials, increased struggles with design-for-manufacturing technology and other issues remain to be solved.
Ted Vucurevich, chief technology officer at Cadence Design Systems Inc., said much work remains to be done on models, which he described as the interface between the manufacturing and design automation worlds. And those models are becoming so complex that they require early, intimate engagement between EDA software developers and process developers, he said, warning that the EDA industry may have begun work on 65 nm two years too late.
Vucurevich said EDA developers must build models that take into account the three-dimensional pattern dependencies from which process variations spring. Then they must identify which patterns can be made to fall within a reasonable level of electrical-parameter variance and incorporate this data early in the design flow. The goal is to avoid having to fix whatever comes out of synthesis and place-and-route with postprocessing reticle enhancement techniques.
"I think 45 nm will be our real problem child," he said. "At that point the pattern dependencies become severe, and we have to move to whole new concepts such as in-situ validation of electrical parameters."
John Martin, vice president of strategic alliances at Chartered Semiconductor Manufacturing Ltd. (Singapore), said Chartered is ready to support designers targeting the 65-nm node. With partner IBM Corp., the foundry is ready to provide Spice models and other forms of design support, with 65-nm multiproject wafers planned for the fourth quarter.
Beyond 65 nm, Martin predicted, the industry will see new materials introduced, particularly in the gate stack, with the attendant learning curves. New transistor structures will emerge as well, he said, to achieve an acceptable combination of drive current and leakage current. And with those changes will come changes in circuit and cell design techniques and in the approach to defect management, along with a new emphasis on process controls.
Further out, Fumitomo Matsuoka, senior department manager at Toshiba Corp.'s System LSI Division, foresees "many roadblocks," including a power-performance crisis. After 45 nm, we will see designs where standby current will dominate the overall power consumption of large chips." Moreover, Matsuoka continued, "the markets we are now serving require a very fast manufacturing ramp. But the very complexity that makes these products possible means that ramping is difficult. Further, costs are becoming huge. Complexity costs money — even the equipment we must buy is hugely expensive. I think maybe we can achieve full production through 45 nm, but to do that circuit designers will have to help with issues like power."
Daniel Gitlin, senior director of technology development at Xilinx Inc., warned that pattern-related variations were increasing, making circuit design and modeling vastly more difficult. At the same time, he said, dwindling supply voltages — decreasing much faster than threshold voltages — have narrowed the design window to the point that only about 0.7 V is left for circuit designers to employ.
"At 65 nm we see a fork in the road," said Gitlin. "Already it has become impossible to continue scaling oxide thickness. Instead, we are turning to mobility engineering and, eventually, to new gate stacks. But these techniques in turn are creating more severe layout dependencies. Yet we will continue. The job of process engineering is to make all the revolutionary things that have to be done appear evolutionary."
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