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Technology Stocks : Applied Materials No-Politics Thread (AMAT) -- Ignore unavailable to you. Want to Upgrade?

To: etchmeister who wrote (15185)	6/4/2005 1:01:27 AM
From: Proud_Infidel	Respond to of 25522

April slump for tool book-to-bill, IC capacity Mark LaPedus EE Times (06/03/2005 7:22 PM EDT) SAN JOSE, Calif. — Amid a drop in overall fab utilization, the worldwide chip-equipment industry posted a book-to-bill ratio of 0.82 in April, up from 0.71 in March, according to VLSI Research Inc. on Friday (June 3). Worldwide fab capacity fell from 83.7 percent in March to 82.9 in April, according to the research firm. Worldwide bookings amounted to $3.7 billion in April, while billings were $4.5 billion for the month, according to VLSI Research (Santa Clara, Calif.) The April bookings were 11 percent below the previous month and down 35 percent from the like period a year ago. Worldwide billings were 23 percent below March and essentially flat from the previous year. "The equipment industry has been experiencing a slowdown in bookings for several months now even though chip makers have been doing well," according to the research firm. "Still, chip makers remain cautious with equipment spending," according to VLSI Research. "In fact, they have cut back on production in order to keep prices at profitable levels. This has pulled down utilization rates below the 85 percent mark. At current utilization levels, chip makers don't see the need for more equipment." In May, fab utilization is expected to climb to 84.4 percent. The book-to-bill ratio is expected to inch up to 0.91 in May

To: etchmeister who wrote (15185)	6/6/2005 1:32:41 PM
From: Proud_Infidel	Respond to of 25522

PSC begins operating second 12-inch wafer fab Hans Wu, Taipei; Carrie Yu, DigiTimes.com [Monday 6 June 2005] Powerchip Semiconductor Corporation (PSC) announced last Friday that its second 12-inch wafer fab (Fab 12B) has begun operation. PSC has scheduled a total investment of NT$60 billion (US$1.9 billion) for the plant and it will have maximum monthly capacity of 40,000 wafers, according to company chairman Frank Huang. With the capacity added from the second plant, PSC will have a total monthly capacity of 75,000 wafers from its two 12-inch wafer fabs by the end of the year, with total capacity increasing to 100,000 in 2006, Huang added. PSC will also spend NT$200 billion (US$6.4 billion) to build two more 12-inch wafer fabs over the next four years, Huang said. The company is now producing commodity DRAM memory at its first 12-inch wafer fab, while the next two fabs will focus on NAND flash memory production, Huang stated. In related news, Huang said PSC will begin test production of wafers using 90nm technology by the end of the year, with volume production commencing in 2006.

To: etchmeister who wrote (15185)	6/6/2005 7:15:33 PM
From: Proud_Infidel	Respond to of 25522

Researchers propose futuristic interconnects for ICs Mark LaPedus EE Times (06/06/2005 5:19 PM EDT) BURLINGAME, Calif. — At the IEEE International Interconnect Technology Conference (IITC) here, researchers presented several futuristic technologies to solve the interconnect bottleneck in chip design. Activated bonding, air gap, carbon nanotubes, molecular wires, optical interconnects and spin-wave buses were among the technologies proposed at the event. During the keynote address on Monday (June 6), Michel Brillouet deputy director of France's CAE-Leti, also proposed biometric and communications-based schemes for interconnects in chip designs. One conceptual interconnect methodology is the so-called "bottom-up" or biometric approach. "It is appealing to translate the example of the highly connected central nervous system, which performs chemically-assembled guided growth, and provides a 3D functionally-assembled network," Brillouet said in a paper at IITC. Another possibly for future interconnects is a shift from current wire-based technology to something that resembles a telecommunications network within a chip — or an adaptive protocol-based communications network. In this case, the CAE-Leti technologist proposed a so-called network-on-chip architecture, which supports routing and switching in the device. Other interconnect technologies have also been proposed. Japan's Fujitsu Ltd. is expected to present a paper on a new breakthrough with carbon nanotubes. In the paper, the company claims that multi-walled carbon nanotubes could offer low resistance in interconnect vias for next-generation chip designs (see May 18 story). Researchers at Georgia Institute of Technology have developed a CMOS-compatible approach for fabricating on-chip microfluidic cooling channels using a spin-on sacrificial polymer material at the wafer level. Separately, Research at the University of Rochester in New York on developing silicon-based building blocks for on-chip optical interconnects is another potential solution. An all-silicon, on-chip optical interconnect is a candidate to overcome the electrical interconnect bottleneck (see May 3 story). The University of California at Los Angeles (UCLA) proposed three technologies for the nanotechnology era: molecular wires, resonant tunneling diodes and a spin wave bus. Molecular wires can be self-assembled onto an underlying structure and have "the potential to operate at the single-molecule level," according to UCLA. "The use of tunneling structures demonstrates another possibility of resolving the interconnect problem by constructing a homogenous cellular antomata like structures, which all local interconnections are achieved via the tunneling between the nearest nano-devices." For long-range interconnection, UCLA proposed spin-wave bus technology. The interconnections between the nano-devices can be accomplished in a wireless manner via the waves," according to UCLA.