Industry faces challenges with new low-k films
Mark LaPedus
EE Times
(06/13/2005 7:43 PM EDT)
SAN JOSE, Calif. — Leading-edge chip makers are moving full speed ahead to deploy next-generation, low-k dielectric materials, but there are still several challenges to bring the technology into mass production for the 65-nm node and beyond.
At last week's IEEE International Interconnect Technology Conference (IITC) in Burlingame, Calif., the Crolles2 Alliance, Fujitsu, IBM, TI, Toshiba, TSMC and others separately presented papers about their future directions for a new class of porous films with k factors down below 2.5. And the semiconductor industry remains bitterly divided over which technology — chemical-vapor deposition (CVD), spin-on, or a hybrid of both — will break the magical 3.0-k factor barrier.
At present, leading-edge chip makers are just barely making chips with first-generation, non-porous films with k factors at about 3.0. Some wonder if the IC industry can make the transition towards the more fragile porous low-k materials at 65-nm and beyond.
"I'm pessimistic," said Neil Hendricks, a semiconductor-materials veteran and principal of consultancy firm Advanced Wafer Fab Materials Inc. (Los Altos, Calif.) at IITC. "Porous low-k dielectrics will have a hard time moving into manufacturing."
The overall goal for the IC industry is to see a 10 percent performance boost with these new, porous low-k materials, said Huey-Chiang Liou, advanced dielectric/CMP materials program manager at Intel Corp. (Santa Clara, Calif.). But even with a mere 10 percent boost, "there are still many challenges" to integrate these films into chip production, he told EE Times.
Still others were more upbeat about low k. Cindy Goldberg, distinguished member of the technical staff at Freescale Semiconductor Inc. (Austin, Texas), said that the tool makers are already capable of delivering new and working porous films with k values down to 2.2.
Low-k or bust
Low-k materials reduce capacitance and propagation delays within the interconnect layers of a device more effectively than mainstream silicon dioxide insulators, boosting overall chip performance in next-generation designs.
But after many years of research and aggressive promotion of new materials, the industry has pushed back its technology road map for low-k processes, and revenues for the technology have fallen short of expectations. The deployment of low-k has been hampered by integration problems with copper and packaging complexities.
In 1999, the International Technology Roadmap for Semiconductors (ITRS) called for lower-k materials with values of 2.7 to 2.2, but the complexity of this technology caused the IC industry to push out those targets to 2007 or beyond.
The industry began working on ultra low-k porous films as far back as the mid-to-late 1990s. "As of 2005, no one is using porous," said Philip Dembowski, global market manager for semiconductor fabrication materials at electronic materials provider Dow Corning (Midland, Mich.). "45-nm is expected to be the first insertion point for porous."
And just how chip makers will deposit these materials is also open for debate. CVD has begun to make inroads at 90-nm, while the rival spin-on technology has stumbled in the early going.
Spin-on is like gallium-arsenide (GaAs) — both technologies are still waiting to take off after years' of false starts and promises, observed Farhad Moghadam, senior vice president of the Thin Films Product Business Group at Applied Materials (Santa Clara, Calif.). And "nobody has put hybrid in production," he pointed out.
Some believe that CVD will dominate at the 65-nm node and perhaps beyond, but don't count out spin-on, especially at 45-nm. "I would not be surprised to see a resurgence in spin-on," said Dean Freeman, an analyst with Dataquest/Gartner in San Jose.
The hybrid island
Japan appears to be leading the way with the various spin-on and hybrid approaches. At IITC, for example, the buzz was centered on a paper from Japan's Fujitsu Ltd. (Tokyo), which believes that spin-on glass is not dead in the water for low-k dielectric applications.
Fujitsu claims to have developed a porous ultra-low-k material for the 45-nm node, based on what it calls nano-clustering silica (NCS) technology. The company is using a spin-on material, reportedly provided by Catalyst and Chemical Inc. (see June 7 story).
To deploy NCS at 65-nm, Fujitsu will devise a hybrid technology, based on spin-on as well as CVD, reportedly based on Applied Materials' Black Diamond technology, sources said. Then, at 45-nm, Fujitsu will move to another hybrid approach, this time, based on a dual spin-on technology via NCS, according to the sources.
Japan's Toshiba Corp. and Sony Corp. also presented a paper on a hybrid approach for the 45-nm node, with a k value at 2.3. Geared for advanced embedded memories, logic, and system-on-a-chip (SoC) devices, the film is expected to use a combination of CVD and spin-on, said Noriaki Matsunaga, a researcher for the Advanced CMOS Technology Development Department for Toshiba (Toshiba).
Toshiba is reportedly working with Dow's SiLK spin-on film for the trench layers. The company has not decided which technology to use on the via layers, he said.
Matsushita, Renesas and other Japanese entities also presented papers on various hybrid approaches. Even Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) presented a paper on a hybrid technology, but the silicon foundry giant is reportedly going with Applied Material's Black Diamond 2 film for the 65-nm node.
Applied will shortly introduce its long-awaited, next-generation low-k technology for the 65-nm node and beyond. Black Diamond 2 supports low-k values down to 2.5, Moghadam said see June 7 story).
Many U.S. and European companies also plan to deploy CVD-based low-k films at the 65-nm node. Some speculate, for example, that the Crolles2 Alliance will deploy the Black Diamond 2 film at the 65-nm node. The alliance consists of Freescale, Philips and STMicroelectronics.
Freescale's Goldberg declined to comment on the speculation. At 65-nm, though, the Crolles2 fab will deploy two versions of low-k, she said. In one version, the Crolles2 fab will extend its current 3.0 low-k film to the 65-nm node. The 3.0 film is also being used at the 90-nm node at the plant.
Crolles2 will also use a porous film with k values at 2.5 for the 65-nm node. Freescale's own 65-nm chips will move into "risk" production in 2006, with volumes slated for 2007.
For the 45-nm node, Crolles2 will follow the same path. It will have two low-k platforms, by extending the 2.5 film down to 45-nm while deploying a new 2.2/2.3 low-k version, she said.
Not all are following the Black Diamond path. At 65-nm, Texas Instruments Inc. is reportedly deploying Novellus Systems Inc.'s CVD-based low-k film. And also at 65-nm, Intel will continue to use the Aurora film, which is supplied by its current CVD vendor, ASM International BV.
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