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Technology Stocks : Applied Materials No-Politics Thread (AMAT) -- Ignore unavailable to you. Want to Upgrade?

To: etchmeister who wrote (16770)	12/6/2005 1:51:31 PM
From: niek	Read Replies (2) \| Respond to of 25522

Press Releases ASML Impacts Industry Roadmap with Immersion and EUV Achievements for 45 nm and Beyond SEMICON JAPAN, Tokyo, Japan – December 7, 2005 – ASML Holding NV (ASML) today announced significant progress towards development of both high NA immersion and Extreme Ultra Violet (EUV) lithography technology: two critical elements of the semiconductor industry’s ability to continue its historical trend of packing more power onto silicon chips. ASML presented the first resist images produced by its TWINSCAN™ XT:1700i. These breakthrough results are made possible by the combination of a 1.2 numerical aperture (NA) catadioptric lens, polarized illumination and water based immersion technology. The lens is performing well within specification and is now ramping up for production. Qualification of the total system is ongoing and the first tool will be ready for shipment by the end of Q1 2006. ASML has multiple orders for this fourth generation immersion tool and expects to ship between 20 and 25 immersion systems in 2006, including shipments to Japan. In addition, ASML marks significant progress on its EUV alpha tool development: collaborating vendors of mask blanks (SCHOTT Lithotec), photomasks (Toppan Photomasks) and optical systems (Carl Zeiss SMT) have been shipping their respective components to ASML. While the assembly of two alpha tools is in progress, the first projection system is being qualified and integrated, an important proof-of-concept for EUV lithography. ASML plans to ship the world’s first 0.25 NA EUV alpha tools in Q2 2006 to the Interuniversity MicroElectronics Center (IMEC) in Leuven, Belgium, and Albany NanoTech at the State University of New York at Albany, N.Y. “The progress achieved in high NA immersion and EUV is compelling because both technologies offer real options for 32 nm lithography and beyond. Also, double exposure/double patterning should be considered to possibly extend 193 nm lithography,” said Martin van den Brink, ASML’s Executive Vice President, Marketing and Technology. “The industry must make roadmap choices and ASML is committed to align to the roadmap of its key customers. As always, we will provide access to early tools for collaborators, vendors and customers. Hands-on experience fosters industry-wide collaboration and will clarify roadmap choices.” About ASML ASML is the world's leading provider of lithography systems for the semiconductor industry, manufacturing complex machines that are critical to the production of integrated circuits or chips. Headquartered in Veldhoven, the Netherlands, ASML is traded on Euronext Amsterdam and NASDAQ under the symbol ASML. Source: ASML

To: etchmeister who wrote (16770)	12/6/2005 3:45:13 PM
From: Proud_Infidel	Respond to of 25522

IBM-AMD, Intel describe 65-nm transistors David Lammers EE Times (12/06/2005 2:47 PM EST) Washington, D.C. — Intel Corp. faced off against the alliance of Advanced Micro Devices and IBM on the stage of the International Electron Devices Meeting here Tuesday (Dec. 6th), presenting 65-nm transistors that rely heavily on strained silicon to achieve sharp performance gains. Intel is in production with several 65-nm processors now, creating an inventory of commercial microprocessor products that will begin shipping early next year. At the IEDM conference, Intel showed die photos of four dual-core microprocessors using 65-nm design rules, which include the Yonah mobile processor and a desktop processor code-named Cedarmill. Sunit Tyagi, senior engineering manager at Intel Technology India (Bangalore, India) presented a 65-nm transistor that achieves a 37 percent performance improvement compared with the 90-nm technology, with a ring oscillator delay of 4.25 picoseconds. Intel made remarkably few changes at the 65-nm node, other than enhancing the germanium content in the deposited SiGe regions at the source and drain region of the PMOS device. The embedded SiGe creates a compressive stress on the PMOS transistor which produces a 30 percent improvement over Intel’s 90-nm PMOS transistor. Tyagi said Intel did not add a compressive nitrde capping over the PMOS transistor, as AMD and IBM do. Intel decided to keep its process as simple as possible in order to keep costs under control, he said, adding that “we achieved our performance goals with this approach.” Andy Wei, a member of the technical staff based at AMD Dresden, described a new process that AMD will first retrofit into its 90-nm microprocessors, and then use in its 65-nm designs going into production in the second half of next year at AMD’s new 300-mm fab in Dresden. IBM will use the new process for its initial 65-nm processors, said Gary Bronner, an IBM project leader at the IBM-AMD alliance based in East Fishkill, N.Y. “Strain engineering has replaced gate oxide scaling as the means to improve performance, because of leakage considerations at the gate,” Wei told a crowd of several hundred at a Tuesday IEDM session. AMD and IBM last year used a dual-stress-liner approach for their 90-nm transistors, putting differently configured nitride capping layers on top of the NMOS and PMOS transistors. At the 65-nm node, the partners added an embedded SiGe layer similar to what Intel used at the 90-nm node. Wei said “a big boost came when we added the embedded SiGe” at the source and drain regions of the PMOS transistor. The PMOS devices now run almost as fast as the NMOS transistors. Wei said the new process will allow design engineers to better balance the size of the N- and PMOS transistors to achieve performance improvements at the product level that he said could approach 50 percent.