SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Semi Equipment Analysis -- Ignore unavailable to you. Want to Upgrade?


To: BMcV who wrote (27484)12/16/2005 2:12:34 PM
From: etchmeister  Respond to of 95743
 
The problem with high u-rates is that they eventually motivate/lead to doublebooking.
There is no reason to believe that NAND flash memory would be an exception (that's what I was refering to as inconsistency).
The concern of doublebooking was voiced by Pam on the SNDK board some time ago.
Even in case it's speculation it's something to keep in the back of your head and pay a lot of attention on how end demand is developing (and the SNDK board is really dedicated in doing this).
I don't know much about backend but Agilent seems to do very well in flash; A's testers are compatible with flash and DRAM - a big plus with regards tp manufacturing flexibility).
I don't know about TER but situation in DRAM is kind of iffy (ironically partially due to Intel chipset dilema - DDR2 is priced lower than DDR); I posted blurb about DRAM output on AMAT board.

12 Dec 2005:

Amid a strong NAND flash forecast, Toshiba may seek additional packaging partners [ Members only ]

but could also be an early warning of a business downturn.
Fortunately we know have DT and almost on weekly base we obtain new datapoints (for example next week Micron)