To: happygambler1934 who wrote (11848 ) 2/18/2006 1:55:50 PM From: NightOwl Read Replies (1) | Respond to of 14464 Hi HAP! Uh... need any help with that "will" of yours? :) Oh well... Seriously though HaP, I think the MoMo Attack will kick in before the start of Q3. Q1 revenues can't help but blow Q1 '05 numbers away. Barring an unexpected bout of bad product, the 0.5M+ sequential revenue growth over 4 straight quarters will convince Galleon, et al, that the waters are ripe for another plunge. Galleon started out with an appetite for 750M+ shares in Q1 '05. They sold off half and are now nibbling again. If as I suspect the commercial sampling of the TXN multi-Mb product starts in Q4, I'm thinking Galleon (and others) will want to be fully loaded to catch the wave. The reason I think TI will start producing samples before the close of Q4 follows this kind of analysis: 1. TI won't want to start using embedded FRAM until their 130nm process equipment has depreciated by at least 2 and possibly 3 generations. Currently their commodity chips are principally made only one generation down the line at 090nm; 2. By 2007 TI will have moved its high volume commodity products to the 065nm process node; 3. By 2008 TI will be testing its high volume commodity products for the 045nm process node; 4. By 2008 TI will need high value product lines, i.e. embedded FRAM products, for it's 130nm equipment which will then be competing against numerous other 200 and 300mm wafer fabs at companies that aren't even thinking about 090nm; 5. But TI won't want to simply wait and flip the switch on volume embedded FRAM production in 2008 without first working with PZT on a volume production line; 6. If TI is to begin sampling embedded FRAM in 2008, they will want to have started commercial standalone FRAM production in 2007 and if they are going to start FRAM production by March of 2007 they will start commercial sample production by Q4 2006. As far as the chip design is concerned I think the unit shown by TI/RMTR last fall was the end of our duo's basic design work. But I doubt that the chip that starts commercial production will be last fall's design. I think that, even before that chip's features were set, TI and RMTR have been sharing ideas with the other major FRAM designers, Samsung, Toshiba, Fujitsu (possibly Matsushita and IFX, but I doubt those two). I believe they will at least attempt to reach an agreement on some basic design standards for multi-Mb FRAM, if not performance specs. But as we know at least in the case of Toshiba and Fujitsu/Epson, the other fabs may not have completed their FRAM design "research and development" phases. In my opinion it is quite likely that some of the "silicon" that RMTR has received from TI over the last year have been test chips built on TI's equipment, but with at least some of the design features espoused by the other fabs with active design programs. No doubt neither TI, nor RMTR, will want to start production with a chip that's DOA in a price/performance comparison to, say, a Samsung chip that's ripe for delivery. This "standardizing" will be the last milestone and its a tough nut to crack. TI isn't likely to try to sidestep the effort unless they are positive they've got the best product ready for production and I don't think that's the case. I haven't searched the JDEC web site for years but it's probably time to do so again. There are other "standards" vehicles that could be used of course, but I'm fairly sure it won't turn out to be the "I'm Intel and you'll do it this way! " industry body & briberama with which we are all familiar... but you can be certain, Samsung will demand a pound of someones' flesh. That's in large part why I am counting on Fujitsu/Epson coming up with the NDRO goods. That would give one of our closer licensee's a leg up on leveraging Samsung into "playing nice" if need be. <Hoo><Hoo><Haa> Anyway... that's how I see it. <g> 0|0