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To: Magrathea who wrote (197328)	5/18/2006 10:31:08 AM
From: _Jules	Respond to of 275872

To: ixse who wrote (197245) 5/17/2006 3:41:39 PM From: Magrathea of 197460 Why can't a coprocessor strategy use a mixed ISA with the handshaking with x86 over the HyperTransport? Maybe I'm thinking way outside the box, but I'm thinking Opteron+HT+Coprocessor makes possible the ability to create well functioning hybrid ISA. Once upon a time, there was a board with a x86 chip you could slot into an 68xxx Macintosh that would allow you to run PC Windows software on the Macintosh platform. An expensive option, but there was a market for it (for a while). -Magrathea Never owned a mac. I did have a 2000 Amiga. I installed such a board, had a 80286 CPU fabed by Harris. Jules

To: Magrathea who wrote (197328)	5/18/2006 10:55:06 AM
From: Rink	Read Replies (1) \| Respond to of 275872

Magrathea, re: Why can't a coprocessor strategy use a mixed ISA with the handshaking with x86 over the HyperTransport? Maybe I'm thinking way outside the box, but I'm thinking Opteron+HT+Coprocessor makes possible the ability to create well functioning hybrid ISA. Once upon a time, there was a board with a x86 chip you could slot into an 68xxx Macintosh that would allow you to run PC Windows software on the Macintosh platform. An expensive option, but there was a market for it (for a while). As I said, not impossible, just unlikely. On die is especially unlikely imo. The IBM/Sony CELL processor is a stripped Power core + a small array of cell's that use part of the Power ISA, IIRC that is. A similar thing can be done with x86 like you suggest, but the cell's would probably be redeveloped at least for this purpose. Before this will ever be done we would probably see it as an off die co-processor (your second suggestion). But even about this possibility we haven't heard a word or suggestion. More importantly I think that two ISA's on one die is just less efficient in more than one way (using more silicon and power than necessary). So in short I think on die Cell coprocessor is quite unlikely. I think instead AMD is more likely to develop it's own cell solution provided that's what the market wants. Possibly even using some Cell / Niagara IP. I think chances are that we are going to see something like this in the long term future but I'm less sure about the how (array of full x86 compliant cores like is the market direction now, or couple of full x86 compliant cores complemented with a nice array of special purpose cores - special purpose as e.g. like the cell core inside the IBM/Sony CELL processor, or an FPGA-like grid, or a vector core). Adding full compliant cores will become less and less efficient I think. So at some moment, possibly even before octal core, we might see a deviation from the route of just adding additional full compliant x86 cores to a combination of a couple of full compliant x86 cores complemented with an array of special purpose cores. EDIT: Afterthought: Maybe we should even think of the additional functions in K8L (Coprocessors for media processing, JVM/CLR acceleration, and TOE, XML or SSL processing) in this way. investorshub.com Regards, Rink