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Technology Stocks : Applied Materials No-Politics Thread (AMAT) -- Ignore unavailable to you. Want to Upgrade?

To: Proud_Infidel who wrote (19010)	5/20/2006 9:25:00 AM
From: Proud_Infidel	Respond to of 25522

IBM researchers probe nanometer-scale memories John Walko (05/19/2006 12:08 PM EDT) ZURICH, Switzerland — IBM has taken the wraps off a groundbreaking project to develop terabit memories based on MEMS technology and referred to as "probe-based storage." The next step is deciding whether to move development to the next phase. Probe-based storage, formerly known at IBM as the "Millipede Project," remains a high priority at the IBM research facility here. It "is part of our efforts into nanotechnology, but at this stage we only have prototypes," Paul Seidler, manager of the Science and Technology group at IBM Zurich Research Laboratory told EE Times. Seidler also spoke at an event commemorating the 50th anniversary of the IBM research facility in Ruesslikon, near Zurich. The laboratory was IBM's first research facility outside the U.S. Four IBM Zurich researchers have won the Nobel Prize, including the 1986 Prize for physics for the invention of the scanning tunneling microscope won by Gerd Binnig and Heinrich Rohrer. Georg Bednorz and Alex Mueller won the physics prize the following year for their work on high- temperature superconductivity. The Zurich team in investigating very-high data rate nonvolatile storage. The work was initially led by Binnig and microfabrication specialist Peter Vettiger. The technology "could eventually evolve as the ultimate memory technology," said Seidler. "While we have working parts and have demonstrated complete data storage systems, there are still technical issues to solve, and the company has made no commitments to a product," Seidler added. "In any case, our role here is to prove that the proof of principle works, [and] it does." In 2002, Vettiger told EE Times it could be two to three years before the team could refine the technology to where it could be considered for manufacturing. The "millipede" chip uses scaled-down MEMS techniques to physically locate and melt holes in a polymer atop a movable silicon substrate. Bit locations are addressed by moving the substrate under the desired read/write head, which is then heated. Static tension causes the head to melt the polymer, making a hole, which can then be read later by the same head when it is not heated. Since the polymer is not destroyed, only displaced, erasure is accomplished by using the head to melt the displaced polymer until it flows back into the hole. Although the read-back rate of an individual probe is limited, high data rates can still be achieved by making use of massive parallelism, noted Seidler. Core components of the probe storage system are a two-dimensional array of silicon probes (cantilevers) and a micromechanical scanner that moves the storage medium relative to the array. The probes are precisely located above the storage medium to ensure that external vibrations are absorbed. The most recent array design consists of an array of 64 by 64 cantilevers (4,096) on a 100-micron pitch. The 6.4 by 6.4 mm2 array is fabricated on a 10 by 10 mm2 silicon chip using a "transfer and join" technique that allows the direct interconnection of the cantilevers with CMOS electronics used to control the cantilevers. In such an array, and with cantilevers about 70 microns long, IBM researchers suggested the system could be used to write data at densities greater than 1 TBit per inch2. "We have shown in experiments that this could be increased to nearer 3 Tbits per inch2," said Seidler. IBM demonstrated a prototype of the storage device at last year’s CeBIT fair in Hanover, Germany, where IBM touted the technology as a potential replacement for magnetic recording on hard drives. It may also have potential as a nonvolatile storage medium in a range of mobile products, including MP3 players, digital cameras and cellphones. The prototype achieved storage and retrieval of data at densities of up to 517 Gbit per inch2. Seidler said mechanical fatigue has so far not proven to be a problem with the system, “but there are other endurance issues we need to look at, notably just how many read and write operations you can achieve with one tip.”

To: Proud_Infidel who wrote (19010)	5/21/2006 1:08:58 PM
From: niek	Read Replies (1) \| Respond to of 25522

EUV litho looks strong for 22-nm node -- and maybe 32, says ASML exec The Semiconductor Reporter May 18, 2006, 6:10 p.m. EDT ARLINGTON, Va. -- Chip makers are divided on whether to use extreme ultraviolet or double patterning immersion lithography systems for the 32-nm node, an ASML executive told an International Sematech forum here today. Martin van den Brink, ASML executive vice president, said memory chip customers seem to prefer EUV for 32-nm processing, while logic customers want single or double patterning immersion at this node. He spoke at the Sematech International Forum on Semiconductor Technology here. The ASML official said water-based immersion will already meet the lithography needs for the upcoming 45-nm node, and is extendable to just below 40-nm. When the industry moves to 22-nm processing, "EUV seems to be the winner," he added. ASML has made significant investments in developing immersion and EUV technology. Both EUV and immersion still face critical issues to be solved, said Scott Hector, Freescale Semiconductor manager of design-for-manufacturing methodology. He said EUV must address flare variation problems, and immersion must tackle the mask error enhancement factor and mask critical dimension control. He said both EUV and immersion lithography camps must work on resist sensitivity and intrafield dose and focus control. As lithography systems grow more complex, affordability becomes a major issue, ASML's Brink asserted. In 2010, a typical EUV tool will be priced at about $40 million, he projected. Affordability also is a huge concern for mask-making equipment, the meeting heard. Freescale's Hector said the industry must spend $250 million to develop new mask patterning equipment. But he said if mask tool makers spend their traditional 8% to 12% of total annual revenue of $800 million, this is "sufficient to produce new tools every three to four years." Shinji Okazaki, director of EUV process technology for Japan's ASET consortium, was not as sanguine. "The mask market size is less than a half that of lithography tools. [External] financial support is indispensable for subsystems development," he warned. "Government funding is needed for the development of subsystems of future masks." Both speakers stressed that consortia are needed to address affordability issues, especially challenges in mask infrastructure, materials, and resists. Lisa Su, vice president of IBM's semiconductor R&D center, reiterated the need for greater collaboration in the chip industry to overcome a growing R&D shortfall. She said the annual semiconductor industry revenue is increasing about 6.5% a year, while R&D expenses are growing at 12.2% a year. "We must collaborate to share the R&D cost as we move to 45-nm and 32-nm nodes," she emphasized. However, she said greater innovation is needed, as well as collaboration. "There is a paradigm shift with innovation overtaking scaling" in continuing down the Moore's Law trajectory, repeating a favorite theme of IBM semiconductor technologists. "Innovation now dominates the performance gains between chip generations," Su said.