Petz, you probably remember seeing it in a Yahoo post that referred to the japanese article:
finance.messages.yahoo.com
Re: Oooooo AMD HOUND Core
by: calzone1 05/31/06 04:05 am
Msg: 1406116 of 1406580
my essence:
modularised cpu,
2 times floating point,
larger cache,
65 nm starting nearly "now",
running for capacity of 50 % marketshare in 2K08 / 09
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I hope you didn't purchase calls based on niceguy's link to this, because...
Unfortunately, the article itself does NOT say that, in fact it shows 65nm launching in Dec/Jan.
Here's the full translated text:
- As for the next of Rev. F with Hound CPU architecture to expansion
K8 "Rev. of the new generation F (Revision F)" AMD which is announced. In the past, AMD the possibility even with the following 65nm process core Rev. G of doing architecture expansion was reported with this corner, but that was the mistake. Rev. G in the almost remains same functional core, as Rev. F the following "Hound (the hound)" does the large-scale architecture expansion of the K8 core in the family. AMD June 1st (the Japanese time June 2nd nighttime) with "AMD Technology Analyst Day", is the schedule which makes the CPU road map clear, but leading that, with the round table which is held in Japan it made part clear.
It is the chart where the bottom compares the CPU core part of AMD. As for this time having become clear, as for the central core in the engineering sample which does not commercialize, differ from actual Rev. G. Most with the Hound core under, architecture is expanded at a stroke.
K8 Processor Cores
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As for PDF editionthis
Dirk Meyer of AMD (darkness mayor) person
Dirk Meyer of AMD (the darkness mayor) the person (President & COO), you talk as follows concerning this chart.
"On in the figure (the CPU core) it is Rev. F. Center with production prototype, it is not Rev. G. As for those which you under call Rev. H, we ' Hound (the hound) ' with are one among the next generation cores which are called ",
Meyer recognized, when the AMD core moves to the Hound family functionally from Rev. F. In other words, with Rev. G which becomes first 65nm process, there are no extensions from of Rev. F. According to a certain AMD authorized personnel, as for Rev. G you say that it is the core which almost is close to optical shrinking. Until now it seems that is supposed, it is not, collects strengthening around the order fetching with of Rev. G with the next Hound core and it is the possibility that strengthening the CPU core function is done. The core generation whom by the way, in the past, AMD Rev. H has explained to the customer presently seems that becomes Hound. Perhaps it is positioning that the result of extensions, stopped being K8 already.
- With Hound core SIMD floating point arithmetic efficiency in 2 times
As explained even in report of the time before, with the Hound core rather substantial extensions are done. Summary of extensions is explained with ?????? CPU which with Spring Processor Forum is released.
Phil Hester of AMD (filling to star) person
"?????? (the CPU core), the basic pipeline today (the core) with it has been similar, but from it expands. Modification of the microprocessor which specializes in item of specification is done. For example, it makes the number of operational units, to the 128bit floating point redouble from the 64bit floating point. This has made the result reflect we learning from the customer of high performance computing. In addition, it does with also SSE order, how many minor instruction set expansion. This is something for especially graphics and security encoding ", that Phil Hester of AMD (filling to the star) the person (Senior Vice President & Chief Technology Officer and AMD) you explain.
The largest eyeball of expansion of the Hound core is expansion of this floating point arithmetic unit. "With favor of bigger floating point unit, 2 times (operational throughput) it becomes", that Meyer talks. With the Hound core, 1 floating point arithmetic pipe is added to the side of the existing floating point arithmetic pipe already.
According to Meyer, you say that the SIMD floating point arithmetic efficiency of SSE reaches 2 times, depending upon this expansion. You say that at double precision total 4 operations of 2 additions and 2 multiplication can be executed in 1 cycle. However, as for Meyer with "as for this we talk SSE operation", it is not expansion of scalar operation, becomes expansion only of SIMD operation. For example, it is not the case that 128bit floating point arithmetic has become possible.
AMD and both Intel, executed by the fact that the SIMD operation of 128bit is really turned, 64bit operational unit two cycles. But, with the Hound core by the fact that the 64bit pipe is added, it reaches the point where SIMD operation of 128bit width can be executed with 1 cycle throughput. Packing converting the 64bit double precision arithmetic 2, because it can execute, logical efficiency of operation reaches 2 times. In case of single precision it reaches 2 times in the same way.
- As for CPU core differentiation to server and Mobile
AMD suggests also that the core of the same company is differentiated to 2 directions.
"Our in the future, design spot of optimization is two. One at the server area, aims for performance, performance/electric power and scalability. For already as for one in the Mobile space, as for this especially you aim high electrical efficiency. These (two) with core technology, it can correspond also the desktop area probably is in addition to both areas of the server and Mobile. Not only data center and Mobile, you think that two core designs can be used even in the desktop. Because you think "that electrical efficiency, with the product of all ranges keeps becoming important, that Hester talks.
In other words, micro architecture itself of the CPU core, is presumed that 2 types of core of high performance and high electrical efficiency and core whose for Mobile electrical efficiency is very high are designed. The Hound core for the server is the core not to be wrong. It becomes the scenario that on that, you bring two cores to also the desktop market. Details are the expectation which with Analyst Day becomes clear, but if you think proper, it does extensions in for the server and preparing the core which pulls up performance. As for performance expansion the possibility of throwing the core which is stopped smallest is high in for Mobile. Perhaps it becomes some division, as for the desktop it is not understood, but both cores exist together.
Though, the core being common, as for other unit there is a possibility of differing. Because AMD is advancing the modular conversion of the unit of CPU.
"We have designed, to moduration converting the future core rather. Because of that, it is possible to make CPU of the new version which responds to the change of needs of the market relatively simply "(Hester)
As for appearance of the new core which increases the variation with modular conversion "it starts from the time frame 2007 - 2008", (Meyer) with you say.
- With the multiple core cash class is deepened
In addition, Hester listed the fact that L3 cash is added with ?????? as one example of the variation of the CPU design. You say that AMD, it deepens cash class in the future, attendant upon the development of multiple core conversion, it focuses to increasing cash efficiency.
Being to think, that "are we in the future important, one of ? items is improvement of cash efficiency. We keep adding the core steadily. Following to that, needs of the memory zone of CPU increase, at the pace which is faster than pace of zone increase of the parallel memory channel. Because of that, as for us it is necessary to do the improvement of memory class. In that case, important thing is improvement of efficiency of cash structure critically. Then, various technologies are researched. In addition, we are advancing the modular conversion of the CPU design even because of that. It being necessary to use what kind of memory technology inside CPU, in order to be able to correspond, to moduration it converts "(Hester)
In other words, because improvement pace of the transfer rate of DRAM is slow, it does not overtake multiple core conversion. Because of that, in the future, unless it has cash which is deeper than presently at bulk, memory access becoming the bottleneck, efficiency stops rising. Because of that, it is the case that it becomes the key whose cash is important.
In addition, the CPU socket one newly there is AMD with Rev. F. In case of the same company, in regard to the circumstances which integrate DRAM interface to CPU, the memory interface of CPU is expanded is necessary also for the socket to renew every. As for socket compatibility the "smallest being, 2 generations" (Meyer) with you say. In other words, the new socket group which is introduced with Rev. F is guaranteed to Rev. G.
- The die/di size of CPU is almost maintained uniformly
AMD advances to multiple core conversion, but die/di size (the area of the semiconductor itself), it is the possibility that almost the same level is maintained. It is the die/di size of AMD CPU where the bottom is supposed. As for the die/di of Rev. F being to be size when the announcing with ISSCC, in product edition there is a possibility of having shrunk more or less, but rough size is the expectation which does not change.
AMD CPU Die Size (Partly Guesstimated)
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As for PDF editionthis
Hester explains the strategy of die/di size of the same company as follows.
"Speaking generally, three it differs to industry, (there is) a sweet spot of die/di size. Our past (CPU) seeing, it is the expectation where it is found that it is three die/di size. When you refer to your figure, (as for the small) die/di under 1st, as for performance it is smallest at entry level. For the market whose cost is important, is general tendency. It is something which central (the die/di of intermediate size), we call price performance or the main stream. With respect to 1st (the largest die/di), being performance oriented, yield rate is restricted. These three bands probably will be over future continue. Strictly, there are various variations, but in general tendency three sweet spots continue ",
In other words, AMD at every CPU type maintains the size of the CPU core, at 3 level, takes the strategy which among those keeps improving performance. This Intel basically is the same.
As for the largest die/di at die/di size approximately of 200 squares mm, presently 2MB L2 cash (1MB×2) dual core K8 system of edition is categorized to this size. But, with the next 65nm process, also Hound of ??????, roughly coming to this position has recognized AMD.
When it rearranges, you start the high performance CPU of the first generation of new architecture or extended architecture, from die/di size of 200 squares mm. With recent pattern, with the derivation from CPU of the die/di of 200 square mm classes, the version which assures the light weight conversion such that cash quantity is decreased comes to the main stream class of 120 - 140 squares mm. And, value class usually becomes CPU of architecture of 1 generation ago. When architecture of 1 generation ago, the main stream is occupied, it is.
When you see in the process generation, 1 architecture it is produced over 2 - 3 process generations, is transferred to the next. This pattern is followed, single core K8 and dual core K8 have traced this course.
"K8 to be made with 130nm process, then, it shrank to 90nm. The dual core is added next with 90nm, dual core K8 faces to 65nm. This is Rev. G. And, New Core appears with 65nm. That this with Hound, moves Hound to 45nm next ", Meyer explains.
Also Hound, as single/dual core K8 is the case that it traces the same course.
In addition, according to Meyer "the average die/di size of CPU little by little is, but it is the prospect that it keeps becoming large. Is ", because needs of the dual core increase, that you say.
As for 3 bands of the CPU die/di maintaining while, average size seems that you see that gradually it becomes large, with the movement of needs to the high performance item.
- The production strategy of AMD which appears in game with new Fab 38
In "Fab 38" name Fab 30 which is modified
As for the notion that where, the same company AMD maintains the same die/di size, furthermore as for average size increases loosely, the fact that also the Fab strategy modifies is indicated. AMD announced the plan "of Fab 38" this is.
AMD has produced CPU with Fab 30 which presently is the German Dresden, adjoining, it has started the work of new Fab 36 where you built. AMD so far limited point Fab for CPU production to just 1 place. In other words, if Fab 36 rode in the track, Fab 30 ??????? doing was normal from CPU production.
New Fab 36 has the manufacturing ability of approximately 1.5 times that former Fab 30. But, if 1 hundred million CPU the capacity which produces (the inside respective company Fab minute in order approximately 8 10000000 it is presumed) to achieve, does not reduce average die/di size in 2008 the same company makes goal it cannot achieve Fab 36 as a single unit. That AMD maintains die/di size the same company continuing, it has meant the fact that CPU is produced with 2 Fab.
As for AMD because new Fab is not constructed under present conditions, production capacity is reinforced, it is necessary to move former Fab 30 to 65nm process. However, several is a hurdle to that. With the facility of Fab 30 where 6 years pass from construction, unless it improves rather, it is difficult to keep following to the process which is refined in the long term. In addition, as for Fab 30 with 200mm wafer Fab, the 300mm wafer equipment of Fab 36 there is no compatibility. AMD, in order equipment introduction and to reduce the cost of process development, equipping Fab 30 conversion, 300mm wafer to Fab has the necessity to convert. Because enormous cost becomes necessary in these expansion, whether or not AMD resigns to there, there was a doubt.
But, if you said from the result, AMD appeared in gamble. You say that large it remodels Fab 30, it is newly born as a 300mm wafer based Fab 38. Because of that, 25 hundred million dollars, the investment which is a match to substantial new Fab construction is done, (in this also investment to Fab 36 expansion is included).
The process technology &Fab presumption road map of AMD
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As for PDF editionthis
Those where this plan shows, AMD being serious, are to be the intention of challenging to Intel. Perhaps, in 2008 1 hundred million calls the number is no more than a passing point. If two Fab work full, because capacity exceeds that. Fab 36, in regard to calculation CPU of present die/di size, 6 10000000/has the capacity which above year can be produced. When the amount which furthermore in foundry Chartered Semiconductor it produces entrusts to that including Fab 38, is included, after 2009 it probably will exceed 1 hundred million. When we assume, that is, goal, is presumed that it is 50% guaranty of market share.
But, AMD does the investment of 25 hundred million dollars anew. It means the heavy baggage that to shoulder sufficient market share and the profit which can collect that are increased. As for AMD, concerning the Fab strategy, you say that it announces with Analyst Day.
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Here's the chart from this very article again:
pc.watch.impress.co.jp
See? Dec/Jan. |
