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To: combjelly who wrote (200051)6/2/2006 11:40:59 AM
From: j3pflynnRead Replies (1) | Respond to of 275872
 
CJ - from RWT: "Based on the cache sizes, the L2 cache is still exclusive of the L1 contents, and the L3 cache is certainly not inclusive (although this does not mean it is exclusive)."

Is there another type of cache? I thought they were either exclusive or inclusive?



To: combjelly who wrote (200051)6/2/2006 11:44:42 AM
From: Joe NYCRead Replies (1) | Respond to of 275872
 
combjelly,

Assuming it even happens. Current L1 has a 3 cycle latency. If that can be cut to 2, or even 1 by halving its size, it would be a win. Especially if the also cut the latency to L2, a capacity miss hurts less on the average.

The only way it would make sense if the L1 became more way. Otherwise, while latency reduction from 3 to 2 would have been important in the past, it is not as important in K8L (or Intel NGA) because of out of order loads.

Joe


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