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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Hans de Vries who wrote (201582)	6/11/2006 6:37:43 PM
From: dougSF30	Respond to of 275872

Disambiguation also has a large impact on apparent latency.

To: Hans de Vries who wrote (201582)	6/12/2006 8:26:34 AM
From: fastpathguru	Respond to of 275872

Hans, re: prefetch vs. OMC: Premises: * Prefetching is used to load a peice of memory into cache before it is actually required by code to hide the effects of latency... * The return on further developments of prefetching approaches zero as average latency approaches cache-hit latency, for any architecture (regardless of whether it has an OMC or not.) Argument: The longer a chip's latency to main memory, the more complex its prefetching mechanism must be to achieve a particular average latency, due to the fact that prefetches must occur earlier to hide the larger memory access latency. Gut instinct tells me that the rate of increase in prefetch complexity rises at a greater-than-linear rate as latency increases. Furthermore, because a chip with OMC needs less "advance notice" of a potential prefetch operation, it can be more accurate even while covering a smaller time window. The longer-latency chip has to guess earlier and therefore will probably make more wrong guesses, with the obvious penalty on cache utilization and memory bandwidth. Thesis: * Opteron will get more bang-for-its-buck out of prefetch development than a chip with an off-board MC, and even if both are developed to the point of perfection, the Opteron's will be simpler. I just wonder, when does it become silly to further develop prefetch logic vs. just biting the bullet and integrating the MC? fpg