Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : ASML Holding NV -- Ignore unavailable to you. Want to Upgrade?

To: niek who wrote (1214)	9/12/2006 5:00:14 PM
From: etchmeister	Read Replies (1) \| Respond to of 42851

SLC v. MLC Flash Memory: Comparing Apples and Oranges * Posted by: Jenn Markey * On: 08/22/2006 15:12:42 * In: Memory * (Comments) Our preliminary analysis of the IM Flash Technologies’ 50nm 4Gb SLC NAND Flash unequivocally proves that it is, indeed, a 50nm device. This moves IMFT to the head of the class in terms of the smallest process lithography. Traditionally, it has been Samsung that has always pushed the process envelope, realizing 4Gb 65nm SLC NAND Flash in the first half of 2006. Conventional wisdom was that this SLC-based strategy, and the corresponding process shrink, was starting to run out of steam. However, IMFT has demonstrated that this is not necessarily the case with their 50nm solution. Die Markings on IM Flash Technologies’ 50nm 4Gb SLC NAND Flash This chip is quite an achievement for several reasons. To start, this is the first actual device that our analysts have seen from the IMFT joint venture – a clear demonstration that this partnership is getting results. Second, according to the 2005 ITRS Roadmap, the Flash Uncontacted Poly Si ½ Pitch (nm) should not be reaching 50nm until 2008. This puts IMFT two years ahead of the ITRS schedule! EETimes picked up details from our press release and put out an article titled "Intel, Micron trail Toshiba in flash density, says analyst", which focused on the single level cell (SLC) and multi level cell (MLC) debate. The article concentrated on the Mb/mm² comparison of the IMFT and Toshiba’s 8Gb 70nm MLC NAND Flash devices. However, this is a bit like comparing apples and oranges, similar to a direct NAND and NOR comparison. They are different implementations that accomplish the same end from an applications perspective. If there is a solution with the required density that meets a company’s needs in terms of cost, performance, reliability, and size, then it is selected, whether it is a direct competitor or not. The advantage of the IMFT solution is cost. With a die size nearly 50% smaller than Toshiba’s, IMFT can produce about 50% more die per wafer. The advantage of Toshiba is density. By offering an 8Gb single die device, Toshiba can offer solutions for the increasing density demand of mobile consumer products. Can IMFT continue to aggressively shrink the process lithography, enabling them to, in the near term at least, outpace competitors, even if they continue to use SLC technology while others migrate, or continue to produce, MLC? Leave a comment semiconductorblog.com