Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: combjelly who wrote (212716)	10/5/2006 7:28:00 PM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Dear Combjelly: With both on a single die, Intel can communicate between the cores without going to the FSB at all. They could do a brain dead design forcing all intercore communication to go to the NB in between, but even they aren't that dumb. Ok maybe the PHB management is. They shown that in the past. Only one FSB interface needs to be done, instead of two. That lowers FSB loads and allows the FSB to be sped up. They could also extend the cache sharing to all four cores. They could also follow AMD to have individual core voltage and clock speed states with one place to control all four cores versus the need for two such places with the dual chip MCM. All of the above lowers TDP and idle power from dual die to single die enhancing performance per watt. Pete PS: While having two dies allow the MCM to seemingly have higher yields, there are losses because one of the two dies is placed bad, has a bad connection or further testing reveals a flaw not found in the first quick test. With two dies, you have a higher chance of this occuring. It is usually not figured when looking at yields, because its overlooked. Whether the two die advantage is high enough to cover the losses is something only those involved with packaging MCMs would know.