3G – is your application processor really necessary? [article circa early 2004 (?)]
Smart phones and multimedia terminals are beginning to emerge as 3G networks finally get established around the world. Nick Flaherty reports
There are a couple of different takes on providing multimedia in phones. The first is the application processor, to handle the video and applications that the 3G technology enables.
Renasas Technology, now celebrating its first full year after the merger of Hitachi and Mitsubishi Electric’s chip businesses, claims to be the dominant supplier of such co-processor, based around its SH3 core with DSP extensions and widely used in the 3G phones in Japan. It is developing a higher performance version of its SH4 core for embedded applications, removing the caches and reducing the power consumption for this market, says Matthew Trowbridge, managing director for Europe at Renasas.
The latest co-processor is the SH-MobileL (SH7322), which starts shipping in June and adds support for high-definition cameras, allowing the direct connection of a 2Mpixel UXGA 1,600 x 1200 pixel camera module, which is expected to be standard in new mobile phones.
This makes it possible to capture and perform electronic-zoom display of high-definition images and enables versatile display features such as superimposed screens through on-screen display and hardware cursor functions, improving the look and performance of the user interface.
It includes 32-Kbyte on-chip RAM with single-cycle access capability and 32-Kbyte CPU cache memory. These memories enable high-speed application execution using Java programs, MPEG-4 moving image processing and MP3 or similar voice processing using the same SH3-DSP core as current SH-Mobile series products running up to 120MHz.
This means that software developed for the current series can be used by the SH-MobileL, enabling shorter system development times to be achieved. A development platform equipped with a keyboard, small LCD panel, and ultra miniature camera is available, simplifying the development of various kinds of multimedia application programs.
Fujitsu has also entered the market with two coprocessors for mobile phones, using another method of integration. Instead of integrating the multimedia functions into the phone chipset, it is adding the DRAM system memory to the media processor package to reduce the footprint.
Fujitsu’s two Mobile Media Processors (MMPs) are aimed at mobile phones and other handheld devices and include MPEG-4 and JPEG hardware encoding and decoding functionality for cameras. They include 2D and 3D graphics accelerators with a 24bit per pixel display controller. The camera YUV interface is supported by both CCD and CMOS camera modules (up to 2MPixel), which can be attached to the MMPs simultaneously, with one active at a time. These have the ability to interface between two LCDs, enabling users to display multiple images simultaneously on two separate screens.
When the internal clock operates at 13.5MHz, and the MPEG-4 codec (QCIF@15fps) is functioning, the device consumes just 13mW (codec core), a much lower power consumption than any other such device. It is also possible to operate the MPEG-4 codec (QVGA@15fps) with the internal clock at 54MHz, allowing not only low power consumption but also high-performance.
“Adding one of these MMPs to the central processor typically found in handheld devices enables the device to handle sophisticated graphics with ultra-low power consumption," said Dirk Weinsziehr, Senior Director Marketing for Fujitsu Microelectronics Europe. "With the proliferation of features in mobile phones and PDAs, there is a growing need for a specialised application processor to handle multimedia functions without sacrificing battery life.”
Built using Fujitsu's low-leakage 0.18_m CMOS (CHECK) process, the processors are housed in 289-pin FBGA packages that also include 64Mbits of SDRAM as a system-in-package, and Fujitsu says mass production will start in September.
Part of the attraction is a fast development time. “The speed of integration from the add-on architecture is evident by the fact that the new Spinner1.1 has already been integrated into multiple form factor platforms just 7 to 8 weeks after we received it back from the fab,” said Werner Sievers, CEO of Zyray Wireless. His latest chip – Spinnerchip1.1 – is being used by Infineon to provide 3G capability alongside its existing GSM and GPRS designs.
Similarly ST Microelectronics has its Nomadik applications processor, which is now in production, and Intel has come along with its Bulverde 3G co-processor to offer similar capabilities of graphics and video via a separate co-processor that uses a 3D graphics core from Imagination Technologies.
But not all the chip suppliers see these separate applications processors as the way forward.
The latest chipset from Agere Systems, called Vision, has an area of the chip dedicated to the GSM capability that cannot be touched by applications, with a separate section of the chip for the higher performance functions, and includes a video accelerator block. This approach allows the software to be separate to avoid problems with the basic phone functions, but also for the power to be managed across both modules to keep the battery life acceptable, says Andy Craigen, director of product marketing at Agere.
Similarly US CDMA technology supplier Qualcomm is looking to get into the European market on the back of the W-CDMA technology. It says 1m 3G handsets have already been shipped in Europe already and predicts there will be 6m shipped this year in Europe out of a total of 15m.
Qualcomm’s 6275 chip, due out at the end of this year, handles HSDPDA and MPEG4 video, with separate DSP blocks for the WCDMA and for the applications, all in a single chip. “Integration is a key strength for us,” said Luis Pineda, vice president of product management for CDMA technology. “It brings a lower cost to our customers, less current and less space requirement to give smaller form factor phones.”
It is moving to a dual-core processor architecture for its 7000 family of devices for next year, he says.
Texas Instruments – already the leading supplier of silicon for smart phone - is using a strategy of multiple cores in a single chip to tackle this market. Its OMAP 2 platform combines a DSP core with a general purpose ARM11 processor and multiple acceleration blocks, all linked by a high speed non-blocking interconnect system which TI is patenting
The OMPA2420 processor has an ARM1136 core running at 330 MHz coupled with a TMS320C55x DSP at 220 MHz, the same structure as today’s OMPA devices. But it adds 2D/3D hardware though the MBX core form Imagination Technologies, the same as Intel, that handles up to 2M polygons/sec, and a camera interface.
The OMAP 2420 adds support for a 4Mpixel camera and full motion video encoding or decoding at rates up to VGA at 30 frames per second with 5Mbits of internal SRAM supporting a VGA display. It also has a video out capable of supporting an external TV display so that a smartphone can play back video on a TV, turning the phone into a more general entertainment device.
“Wireless technology provides a low-cost, low-power platform to make it practical to expand the value of a cell phone beyond voice,” said Rich Templeton, now chief executive officer of Texas Instruments. “We’re not far from the day when smartphones are projected to outsell laptop and desktop computers combined. Last year, camera phones became the best selling cameras outpacing digital still cameras, which themselves surpassed film cameras for the first time.”
The OMAP2 chip aims to increase video performance by four times and 3D graphics capability by 40 times over the previous generation by adding new accelerators into the chip. This level of performance is going the needed in the next year, says Templeton.
“It took about 10 years to really develop digital voice and sleek form factors,” he said. “Camera phones have become very popular in just two years, and we’ll see the same thing happen with other features such as videophones and digital TV in just one year.”
But one of the most interesting developments comes from Ceva, which took over Irish IP supplier Parthus a year ago. It has developed an architecture for a digital signal processor called Ceva-X that uses a hybrid of very long instructions words (VLIW) and single instruction, multiple data (SIMD) techniques and can be implemented with different numbers of multiple accumulate engines for differing levels of performance.
Around that it has developed a new approach to handling video. Instead of doing all the calculations needed for the discrete cosine transforms (DCT) etc on a block of pixels in the encoding and decoding process, the algorithm looks up the value in a database. If the value for that block is not available, then it does the calculation, but the technique gives a significant speed improvement.
On Ceva’s existing Teak-based DSP core, this approach means that decoding 30 frame/s MPEG4 video takes just 45MHz, while encoding it takes just 90MHz. This means that other functions can be run on the DSP at the same time, or the chip can be run slower to save power, says Gideon Wertheizer, chief technology officer at Ceva.
Integrating this kind of capability into a chipset will allow power consumption to be dramatically reduced, and this is going to be one of the key differentiators for 3G phones and one of the toughest challenges. It won’t be seen by the users, as phones without satisfactory battery life will not be bought by the network operators, but it will delay and reduce the range of handsets that are available. Neither approach has the upper hand as yet, but system designers have plenty of options for their next terminal designs.
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