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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Sarmad Y. Hermiz who wrote (217818)	11/28/2006 8:36:12 PM
From: dougSF30	Read Replies (1) \| Respond to of 275872

I believe what they are saying is something like this, but I may be wrong: Picture a grid, with small circles centered at each grid point. The grid is the "metal layers", the circle size corresponds to transistor size. As 90nm has been around, the circles have occasionally been shrinking, while the grid has remained the same. When the new 90nm parts are released (soon?) the circles will be so small that they will actually fit on a smaller (65nm) grid, and the first 65nm parts will use the same circles. So they are arguing that the 90nm parts to arrive soon will actually feature 65nm transistors, as it were. It is a bit strange, then, that these 65nm transistors, on the finer grid in the first 65nm parts, will lead to slower overall parts, but whatever. So the chip size will shrink by the usual 57-60% factor. The interesting thing is that it could have been shrinking all along during the 90nm transistor shrinks, but it is a pain to do all that work, and easier to leave the grid alone while improving the transistors, which is what they did. In Q2, they hope to squeeze out a tiny bit more performance by incorporating the SiGe strain they've been talking about. What isn't quite explained by this story is why the first 65nm parts don't run at >= the speed of the last 90nm parts, and why they are not predicted to beat them even in Q207. After all, if they are using the same transistors with tighter (shorter) spacing, then what is causing the slowdown, and a relative slowdown predicted to remain for a few quarters? Increased interaction effects due the tighter spacing? Thermal constraints? (roughly same power in a smaller area). I still wonder to what extent the transistors are actually "the same" vs. using "the same technologies"

To: Sarmad Y. Hermiz who wrote (217818)	11/28/2006 8:38:48 PM
From: eracer	Read Replies (1) \| Respond to of 275872

Re: Does that mean there will be more chips per wafer? Yes, many more per wafer. Perhaps 2x or more. A straight shrink would put Brisbane around 100-110 mm^2 instead of the current 183 mm^2. If AMD improves cache density beyond that of just the node change then sizes of 90 mm^2 or smaller are possible. That could mean a flood of cheap chips which could hinder Intel ASPs even with Core 2.

To: Sarmad Y. Hermiz who wrote (217818)	11/28/2006 9:23:26 PM
From: Joe NYC	Respond to of 275872

syh, The overall chip size is a function of the largest of 2 components - transistors and metal interconnect. AMD claims continuous improvement in (among other things, shrinking the size of) transistors. But the metal layers change infrequently - in infrequent large jumps. The current large jump is from 90nm to 65nm feature size. Since the overall chip size is the function of the larger of the 2 (transistors, metal layers), the changes to the tranistor size did not matter from the point of view of the overall die size. But now, the the "bottleneck" - metal layers are shrinking, so now the chips will finally shrink. (reading the other replies, eracer gave you estimates of the die sizes). So now, with 65nm chips being processed (arriving to be available for sale in December), AMD capacity will grow fairly substantially, and costs per chip go down as it transitions to 65nm. You had said chip size would not shrink until metal layers are made smaller. So will the layers be smaller in q1 ? And if in the first generation the transistors are the same, do the metal layers have to stay same (as in 90 nm). Meaning that during q1, there will not be cost savings from 65 nm ? Well, theoretically, it is Q4 when the new chips arrive, but percentage-wise, vast majority of the chips sold in Q4 are going to be 90nm. The ratio of 65nm to 90nm will grow, as AMD will reduce 90nm wafer starts and increase 65nm wafer starts. As far as chip size of a typical chip (Brisbane), that will stay the same size forever (until it is discontinued) because I believe AMD doesn't do optical shrinks. Intel used to, but I doubt they do it any more. This particular chip (Brisbane) will experience large jump in dies per wafer, and cost reduction compared to current mainstream part (Windsor), But there will be no more large jumps throughout its life (only tiny cost savings as yields improve over time). But the cost savings need to be kept im perspective. There may be .5M 65nm chips sold in Q4, 14.5M 90nm chips. The cost savings are only on the .5M of the 15M (estimated) total units compared to 90nm equivalent (Windsor). As far as cost savings in Q1, they are not from the tiny yield improvements of Brisbane, but from transition from Windsor to Brisbane. My WAG is that about 1/3 of the units shipped in Q1 will be 65nm. Joe