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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: dougSF30 who wrote (219034)	12/5/2006 3:03:04 PM
From: jspeed	Read Replies (1) \| Respond to of 275872

edit: They are not hiding it. You can purchase a detailed breakdown from Semiconductor Insights (for a handsome fee no doubt). The fact that these guys gave AMD's 65nm process their award should be enough to tell you that it's good. edit: semiconductor.com Semiconductor Insights Logic Detailed Structural Analysis report provides a thorough analysis of the silicon processing steps involved in the construction of this innovative IC. Our report is a comprehensive examination of each level of the fabrication process from passivation to wells. The Detailed Structural Analysis of the Advanced Micro Devices Opteron Rev G 65nm Microprocessor includes the following information: Package and Die Overview - Front and back package photos, package x-ray, and a die photo - Package Cross-section Device Measurements - Die size, die thickness - Number of poly / metal layers - Critical horizontal and vertical dimensions Horizontal: - Minimum metal line width(s), space(s) and pitch(es) - Minimum poly line widths, space - Minimum via and contact sizes and overlap rules - Minimum contact to gate spacing - Minimum NMOS and PMOS gate lengths - SRAM cell area - Standard gate area (a single two-input NAND) Vertical: - Thickness of layers comprising each metal and poly level - Isolation, inter-level and passivation thickness - Isolation edge geometry - Gate dielectric thickness Cross-Sections and Images - Cross-sections of following critical features: NMOS and PMOS transistors, vias, contacts, metalization, inter-metal dielectrics, and passivation - TEM image of core logic transistor gate and contact structure - HRTEM Lattice fringe image of core logic gate dielectric thickness Device Topography - SRAM - High magnification SEM images of poly - Core Logic - High magnification SEM images of poly - Bond pad - Die Corner - Power Bus Substrate Overview - Well and substrate doping profiles from SRP Passivation and interlevel dielectric profile - Identification of dielectric systems such as FSG, CDO, and barriers Techniques Applied: - Cross-section - De-layering - SEM - TEM - SRP Analysis of the above techniques and images will include: - Identification and analysis of key materials - EDS analysis of silicides - Identification and analysis of dielectric layers - dielectric type and deposition method for inter-level dielectrics and passivation - Identification and discussion of unique device features and innovations - Analysis of reliability of process - Identification of process artifacts - Comparison of device to previous process generations as applicable A comparison of device to competing technologies is also given. This report comes with 5 hours of analyst time.

To: dougSF30 who wrote (219034)	12/5/2006 3:08:49 PM
From: FJB	Read Replies (1) \| Respond to of 275872

Doug, You have exceeded the speed limit. No more posts today, or say goodbye for 48hrs. Thanks for your cooperation!

To: dougSF30 who wrote (219034)	12/5/2006 3:42:39 PM
From: rzborusa	Read Replies (1) \| Respond to of 275872

Doug, As an Intel long wouldn't you be happy if it had taken AMD longer to bring up 65nm? Don't answer yet. I will vote against the 20 speedlimit out of a sense of fairness to you. It seems a word count would be more appropriate but way too difficult. I don't begrudge you, and am glad you keep your posts short and to the point, hence numerous. As I understand it, the moderator is not compelled to act. Many including you have been quick to request moderation. It is good to disagree. We get the thread we deserve.