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To: Hans de Vries who wrote (219429)12/7/2006 11:53:12 AM
From: MagratheaRead Replies (1) | Respond to of 275872
 
Ok, I'll bite.

Why is the integrated Northbridge (ODMC) not expected to scale?

Is it a function of signal & power to go off chip?

-Magrathea

Sure has been a dark morning for tech, today.
Is it just people taking profits once the slide started?



To: Hans de Vries who wrote (219429)12/7/2006 12:31:05 PM
From: kpfRespond to of 275872
 
Hans

Keep in mind that some parts like the integrated "Northbridge"
functions do not scale at all,...


As a suggestion, adding "at this point in time" would prevent from a possible misunderstanding. I don't think you wanted to insinuate the parts are not shrinkable at all?

However, great to see you posting here. I appreciate your work since many years.

K.

Edit: While we are at it: Are your able to figure out additional rendundancy in the 65nm-layout you have seen vs. 90nm, in particular in cacheland? TIA



To: Hans de Vries who wrote (219429)12/8/2006 2:41:18 PM
From: RinkRead Replies (1) | Respond to of 275872
 
Hans, just a little detail. Talked some more with CJ and it looks to us that this example of ideal scaling does not yet take into account the somewhat denser cache. From your die picture the 512KB L2 still looks to be some 5x smaller than the 1MB from the rev F picture. Guess we're still pretty curious as to what the actual die size of Brisbane will be...

Regards,

Rink