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To: pgerassi who wrote (219519)12/8/2006 1:48:12 AM
From: NicoVRespond to of 275872
 
I thought the pad limitation was still there with flip chip packaging. After all, you still have to make good contact with the pins. But indeed, I was mainly thinking of wired bonded CPUs, and the fact that north and southbridges historically haven't been built on leading edge process because of being pad limited.



To: pgerassi who wrote (219519)12/8/2006 5:18:01 AM
From: PlisskenRespond to of 275872
 
Would it be correct to assume that these areas are not as prone to defects as the smaller structures of core and cache?


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