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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Sarmad Y. Hermiz who wrote (219875)	12/10/2006 12:54:38 AM
From: economaniack	Read Replies (2) \| Respond to of 275872

Sarmad, "But I think the factors I outlined are more relevant to whether AMD will clobber Intel or not." AMD is in the middle of a process ramp. They are on a 4 year old core. They have just spent 5 times their current assets to buy a company which is probably losing money. At this point I will be happy if they get to 65nm, get out ATI's new chipset and graphics core, and get the new (K8L?) core out next summer without facing a meaningful chance of bankruptcy in between. Clobbering Intel is not on my most hopeful list of outcomes. I think if things go well, they can hold server share and gain some share in notebooks which are high enough margin that they could have modest continued revenue share gains, especially if the 65nm ramp allows additional unit and especially dual core output to compensate for declining ASPs. I think at 20 AMD is priced for BAD THINGS, and only moderately horrible will be something of a relief. I really like the long term prospects for a dedicated mobile core and integrating ATI tech so if they lose a little ground in 07 but keep those things on track I will be happy. If they start actually losing money again in 07, something I don't view as terribly unlikely unfortunately, I will be unhappy. In between I think it is easy to get waaay too excited about a dime of earnings either way. e

To: Sarmad Y. Hermiz who wrote (219875)	12/10/2006 4:18:04 AM
From: Magrathea	Read Replies (2) \| Respond to of 275872

Sarmad:[1]And I think there is an implied assumption that a 65 nm part has the usual shrink factor (close to 55% of the 90 nm part). And [2] also that the yield (in % good die from the wafer) is similar to the 90 nm parts. There is further the assumption [3] that the 65 nm parts are of equal quality and ASP compared to 90 nm parts. I think these 3 assumptions are false. [1]Hans has already established that some parts of the K8 will not shrink with the node -- the ODMC is one he singled out. It has something to do with signal strength and drive currents needed to communicate with memory. [2]Makes no sense. Let's assume a 90nm design fits 200 die on a wafer. And that it "yields" 80% good die at saleable specs. That is 160 good die at ASP X. If [2] is valid, then 65nm design would fit approximately 400 on a wafer. At 80% yield, that would mean 320 good die per wafer. But it makes ECONOMIC sense to start producing 65nm when you can yield >160 per wafer (at the same bin splits) which implies a yield of only 40%. Let's suppose AMD gets their 65nm process up to 60% yield or 240 good die/wafer. Each wafer would be yielding more die than the 90nm process could theoretically make. Is ANYONE going to say "Nope, the percent yield of 65nm is not equal to the 90nm process, 65nm is just not ready for production??? At 60% yield, 65nm would be producing 50% more die per wafer than the 90% on its best day. What are you waiting for? [3] Why should new parts on a new process be expected to be better than an older process tuned with the experience hundreds of thousands of wafers? The physics get better, but the margin for error gets worse. An alignment error at 90nm that may take a chip down one bin might take it down 3 bins at 65nm. It takes time to tweak the production line. AMD takes 100s of measurements on every chip from every wafer throught the line learning what machines to tweak to increase quality. It takes some time. Furthermore, what is your measure of "equal quality" compared to 90 nm? Top Bin? Bin Distribution? Sweet Spot? Bin Distribution at a given TDP? For the moment I'll grant you that 65nm doesn't seem to beat 90 nm in the top bin. The jury is still out on Bin Distribution and Sweet Spot. And AMD says 65nm is a big improvement over 90nm in "performance/watt" which I take to mean a better bin distribution at a given TDP. Dirk at the June Analysts meeting said that AMD was driving 65nm not for the top bin, but for the mass market because "that's where the volume is." A lot of hand wringing back then that something must be wrong with 65nm if it doesn't beat 90nm in the top bin. Others said 65nm might be targeted for power and yield. Here we are 6 months later and the argument has not changed. We'll just have to see what is on the shelves in Q1. What the heck is meant by "Mature Yields" anyway? Is it some magic % of the wafer that meets minimum specs? My argument at [2] shows that a fixed % makes no economic sense. Is it Number (not percent) of good die per wafer? AMD hasn't said, but their own charts from analyst meetings and publications don't lead much support for this with a flat "Mature Yield" line. What the heck happens to a process once it reaches Mature Yields? Those same charts don't tell you! Can we really expect that once a process reaches "Mature Yields" that there is no improvement? Or they stop using it?? Hardly. AMD's charts have some pretty steep slopes intersecting the "Mature Yield" line and then we see nothing more. So if any weight is going to be given to those charts, we have to be concious of the question what happened past where mature yield was reached. If we saw where those yield curves really plateaued, perhaps each at a different plateau!, we might know a lot more about actual yield - which AMD doesn't want us to know. The only definition of "Mature Yield" I found through Google is this one: sst.pennnet.com Aug 2006 AMD defines mature yield as the yield at which a technology becomes economically viable to produce in high volume. I don't know AMD defines it that way. I don't know where the author got that or whether it is his interpretation. But that is a definition that makes sense when running a factory. -Magrathea