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To: pgerassi who wrote (219985)	12/11/2006 8:31:36 AM
From: Sarmad Y. Hermiz	Respond to of 275872

Dear Pete, It is important to omit pieces of assumptions. I repeatedly said "like for like" comparison when I spoke of ASP's. Yes, the reason revenue and profits have not become negative is that the old parts are EOLed. Now let's move on to AMD's 65 nm parts. They are not at higher bins. They are just variants of the middle bin 90 nm parts. Therefor, I'm predicting they will not bring higher margins. Anyway, I think my point should have been clear after so many iterations. I think you still disagree with it, though. We'll see when q4 margins are reported. Sarmad

To: pgerassi who wrote (219985)	12/11/2006 1:28:42 PM
From: FJB	Read Replies (1) \| Respond to of 275872

Start-up claims gate leakage breakthrough using ‘superlattice’ layer Print Monday, 11 December 2006 A materials start-up just out of stealth mode, MEARS Technologies has claimed it has made a significant breakthrough in reducing gate leakage by as much as 60 percent in NMOS transistors and up to 80 percent in PMOS transistors, using conventional process techniques while introducing a silicon laminate, or ‘superlattice,' layer with no new materials introduced. The ‘Silicon-on-Silicon' solution is claimed to work due to the understanding of quantum mechanics in deep-submicron devices that employs a form of band engineering within the silicon as a channel replacement while maintaining or even improving drive current for a variety of deep sub-micron processes. The company also claims compatibility with strained silicon and silicon-on-insulator (SOI) baseline CMOS processes. "The ability of the industry to respond to these demands continues to depend on the electrical properties of a single material - silicon," stated Robert J. Mears, founder and president of MEARS Technologies. "As chipmakers attempt to squeeze more performance out of their transistors, the fundamental properties of silicon and its native oxide have become the limiting factor. And while some approaches have been successful in addressing performance requirements, power issues continue to exist. Through a new approach to silicon engineering, we are able to alter the properties of the silicon to improve the power efficiency and speed of transistors manufactured using deep sub-micron process nodes such as 65nm, 45nm and beyond, while maintaining compatibility with standard CMOS manufacturing equipment that is used for the vast majority of today's semiconductors." Mears Technologies has already teamed with ATDF, Lawrence Semiconductor Research Labs, Evans Analytical and Cornell Center for Materials Research. fabtech.org