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To: niek who wrote (1312)	12/12/2006 10:21:17 AM
From: niek	Read Replies (1) \| Respond to of 43535

AMD and IBM to use immersion lithography for 45-nm process in 2008 The Semiconductor Reporter December 12, 2006 SAN FRANCISCO -- While some other chip makers, including Intel and TSMC, intend to start manufacturing 45-nm-generation ICs without the aid of immersion lithography, IBM Corp. and Advanced Micro Devices Inc. intend to start manufacturing using immersion techniques in 2008, with the first products to be available in mid-2008, the two companies -- which work together on process technology development -- said today at the International Electron Device Meeting here. Still, Texas Instruments Inc. may be among the earliest of the major chip makers to start using immersion lithography. TI said earlier this year that it plans to use water-based immersion lithography for 45-nm manufacturing starting in early 2008. The mid-2008 time frame matches up with the timing that AMD has been talking about for its first move to 45-nm process technology, indicating that immersion lithography will be a part of AMD's 45-nm strategy from the beginning. Intel earlier this year said that it plans to introduce 45-nm parts in late 2007 made without immersion lithography. Taiwan Semiconductor Manufacturing Co. Ltd. has said that it expects to introduce immersion as a second phase of its 45-nm process roadmap, but that it will start making 45-nm chips about the same time Intel does, using dry lithography. AMD and IBM are also describing today ultra-low-K interconnect dielectrics that they expect to use for the 45-nm process in 2008, as well as new strain techniques. A high-k gate dielectric was not mentioned as an element in the first AMD/IBM 45-nm process. "As the first microprocessor manufacturers to announce the use of immersion lithography and ultra-low-K interconnect dielectrics for the 45-nm technology generation, AMD and IBM continue to blaze a trail of innovation in microprocessor process technology," said Nick Kepler, vice president of logic technology development at AMD. "Immersion lithography will allow us to deliver enhanced microprocessor design definition and manufacturing consistency, further increasing our ability to deliver industry-leading, highly sophisticated products to our customers. "Ultra-low-K interconnect dielectrics will further extend our industry-leading microprocessor performance-per-watt ratio for the benefit of all of our customers," Kepler said. "This announcement is another proof of IBM and AMD's successful research and development collaboration." Immersion technique will give AMD and IBM manufacturing advantages over competitors that are not able to develop a production-class immersion lithography process for the introduction of 45-nm microprocessors, the two companies said. For example, the performance of an SRAM cell shows improvements of about 15% due to this enhanced process capability, without resorting to more costly double-exposure techniques, they claimed. The use of porous ultra-low-K dielectrics to reduce interconnect capacitance and wiring delay is key to improving performance and lowering power dissipation, AMD and IBM noted in describing the development of an ultra-low-K process integration that they said reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength. The ultra-low-K interconnect was said to provide a 15% reduction in wiring-related delay as compared to conventional low-K dielectrics. "The introduction of immersion lithography and ultra-low-K interconnect dielectrics at 45 nm is an early example of the successful transfer of technology from our ground-breaking research work at the Albany Nanotech Center to IBM's state-of-the-art 300-mm manufacturing and development line at East Fishkill, New York, as well as AMD's state-of-the-art 300-mm manufacturing line in Dresden, Germany," said Gary Patton, vice president, technology development at IBM's Semiconductor Research and Development Center. "The successful integration of leadership technologies with AMD and our partners demonstrates the strength of our collaborative innovation model." Other partners in the process development partnership include Samsung and Chartered Semiconductor Manufacturing. The continued enhancement of AMD and IBM's transistor strain techniques has enabled the continued scaling of transistor performance while overcoming geometry-related scaling issues associated with migrating to 45 nm process technologies, the two companies said. In spite of the increased packing density of the 45-nm generation transistors, IBM and AMD have demonstrated an 80% increase in p-channel transistor drive current and a 24% increase in n-channel transistor drive current compared to unstrained transistors. This achievement results in the highest CMOS performance reported to date in a 45-nm process technology, the partners claimed.