Robert, not sure why I should do your homework for you, but here you go. Looks like you owe alan an apology.
27.3 High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography, S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite*, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C-H.J. Wu, A. Gabor, T. Adam, M. Belyansky, L. Black*, S. Butt, J. Cheng*, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher*, A. Frye, S,Gates, H. Gossman*, S. Greco, S. Grunow, M. Hargrove*, J. Holt, S. Jeng, B. Kim, D. W. Landers, G. Larosa, Lea, X. Liu, N. Lustig, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, C. Prindle*, R. Pal*, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C.Y. Sung, C. Tian, R. Van Den Nieuwenhuizen*, H. Van Meer*, A. Vayshenker, D. Wehella-Gamage, J. Werking*, R. C. Wong, R. Augur*, D. Brown*, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning*, S. Sankaran, D. Schepis, R. Wise, C. Wann, T. Ivers, P. Agnello, Advanced Micro Devices Inc., Hopewell Junction, NY, *SRDC, Hopewell Junction, NY
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain, iii) a functional SRAM with cell size of 0.37µm2, and iv) a porous low-k (k=2.4) back-end dielectric. The list of FET-specific performance elements includes enhanced dual-stress liner, advanced eSiGe, stress memorization, and advanced anneal. The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840µA/mm/1240µA/µm respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0.
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