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To: Tenchusatsu who wrote (225641)2/9/2007 12:27:08 PM
From: dougSF30Respond to of 275872
 
There is a quad-FSB chipset coming out from Intel which will support Tigerton, Intel's direct response to Barcelona.

Minor quibble: Tigerton isn't so much a "direct response to Barcelona" as it is (accompanied by its chipset) the first 4S-capable Core2 part.

Barcelona is AMD's first QC part, and it comes in 1S, 2S and 4S flavors. Intel has 1S and 2S QC C2D parts, and Tigerton & chipset will extend this to 4S, where Intel only has a Netburst DC solution currently (Tulsa).



To: Tenchusatsu who wrote (225641)2/9/2007 12:39:46 PM
From: fastpathguruRead Replies (1) | Respond to of 275872
 
That's not true. Bigger caches and everything that takes advantage of it makes a lot of sense in 4S systems as well. Think about it; the processors can spend less time accessing the memory if more of their working sets fit in their caches.

Agreed... Especially when bandwidth between sockets/chipset is lacking.

There is a quad-FSB chipset coming out from Intel which will support Tigerton, Intel's direct response to Barcelona. Sure, it's not cheap (in terms of cost and power), but just like the multi-chip module concept, it's a pretty good stop-gap measure until Intel finally gets rid of the FSB.

Fair enough, although cost is going to hurt bad, I think... High MB complexity, high R&D, very low volumes. Someone has to eat that cost. What's the memory bandwidth of the Quad FSB chipset?

fpg