SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: Dan3 who wrote (225705)2/11/2007 2:54:51 AM
From: Ali ChenRead Replies (1) | Respond to of 275872
 
"That core to cache choke point is so overwhelming that the connection to outside memory traffic is rarely relevant - chopping that connection's speed in half has about a 3% to 5% affect on overall performance (populating only one memory channel)."

Your conclusion is not warranted. It simply means that the latency to main memory is much more important than bandwidth on the workloads you have in mind. If a processor stalls due to a need of 16 bits of data, and the next data hazard is not located sequentially in memory, supplying 64 bits or 128 bits at once does not improve any performance, and even can have an adverse effect by thrashing already cached data.

Cheers,

- Ali