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To: muzosi who wrote (227350)	3/3/2007 11:44:26 PM
From: Ali Chen	Read Replies (1) \| Respond to of 275872

"if you leave any other timing problems to be discovered by back-annotated simulations (as opposed to analytically solving them) i'd pity your boss." Analytically solving post place and route timing? What kind of nonsense it is? Regarding the use of back-annotated simulations, it is frequently the fastest way to determine the actual name of flip-flops that might be subject of exclusion from setup and hold violations in blocks of clock domain crossing. There are many different kinds of timing "problems", actual I/O timing for example. "You have never done a "par -n 10"" You may have a point here, I never done this. Regarding your other suggestion about affordability of additional ModelSim licenses, they do cost, individually, and a lot. In any case, different test vectors would create different dynamic structures in memory, so it is still not the same as multiple copies of the same application with the same data set. "i think you should see if you can work with some non-toy problems first" Considering that I had to deal in the past with complies that took 18-20 hours to PAR, you tell me... In any case, I think it is enough for a pissing contest. I still believe that I presented a solid case that SPECxx-rate metrics is not the best metrics to evaluate performance of individual workstation, multicore or not. All your/Pete/fpg counter-arguments have been proven to be false or erroneous or irrelevant. - Ali