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To: DDB_WO who wrote (228480)	3/20/2007 9:34:18 AM
From: combjelly	Read Replies (1) \| Respond to of 275872

"A K10 MCM would cause new problems, even not related to probably missing MCM experience" A CPU package is an extremely complex device. There are about as close to being an MCM as you can get with a single piece of silicon. All the major problems have already been solved, sticking another piece of silicon on there isn't a big deal. "but to simple stuff like the necessity to feed all needed different voltages (via enough power pins) to the multiple power planes present on the MCM." That problem had already been solved for Barcelona. There isn't anything different that would need to be done for an MCM. "From the I/O POV the inter-chip communication would be ok (there are 4 HT links on each die and finally only 3 have to go out of the current S1207 package, leaving 3 HT links unused) but the cache coherency traffic (now caused by 8 cores instead of 4) and mem bandwidth will become even more of a bottleneck." Same problem with two socket servers. With DDR3 available, memory bandwidth should only rarely be an issue. So, yeah, a monolithic 8 core would have an advantage in performance for cache coherency reasons. The performance hit might be lower because the electrical issues are more constrained which could allow for faster cHTT speeds. And the MCM would have an advantage in time to market. Given there isn't any need to change the silicon, this should be a simple choice. MCMs aren't the challenge they were 20 years ago. Neither from a cost nor a production point of view. They are routinely used in cell phones, for example, which is a very cost sensitive market.