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To: Magrathea who wrote (228569)	3/20/2007 5:25:33 PM
From: dougSF30	Read Replies (1) \| Respond to of 275872

Are you saying that Pete is off by at least a factor of FIFTEEN? Wow, who would've guessed? Oh, that's right, I did.

To: Magrathea who wrote (228569)	3/20/2007 5:52:00 PM
From: Saturn V	Respond to of 275872

The Thermal Conductivity for Silicon is probably an under estimate! The handbooks typically quote conductivity for standard undoped Silicon which is a poor electrical conductor. Today the Silicon Wafers used for high performance processes are extremely heavily doped, which dramatically lowers the Electrical Conductivity and should have a modest improvement in the Thermal Conductivity as well, compared to undoped or lightly doped silicon.

To: Magrathea who wrote (228569)	3/20/2007 7:15:37 PM
From: pgerassi	Respond to of 275872

Dear Magrathea: The current 300mm wafers in use likely tend to the smaller thicknesses. The thicker ones are for high voltage RF type tasks. With the maximum voltages being less than a few volts, even the 20nm thicknesses will be more than enough. And thus they would further cut the percentage even more (down to 0.3%) Besides the 0.014W/(cm-K) is for amorphorus SiO2. Cystalline SiO2 formed by the injection or diffusion of oxygen in crystalline silicon has a higher thermal conductivity. Note that SiO2 is also used in all layers including the many metal ones and there is more than 200nm of it. Lastly, because all current CPUs are of the flip chip type where the connection bumps are formed on the top side which is then flipped over and bonded to the substrate. The back of the die (wafer) is then connected to a HSF or IHS that carries away most of the generated heat. A small portion is also conducted through the bumps and into the substrate and then into the MB. For diodes and resisters, those leads dissipate up to 50% of the generated heat. Removing the IHS or with some mobiles on S1 expose the bare die, the thermal resistance is much less to a highly efficient HSF than a IHS would allow. The cost is that the die is more easily damaged without an IHS. In general, most assemblers have little problem with bare die backs. Its the ham handed DIYs that typically damage the dies. Past experience is that the percentage of them is quite low. So if Intel is that worried about the little thermal resistance of the thin oxide layer, then they should immediately eliminate all IHSs from their CPUs. Going by their actions and not their words, there is no problem. Even with your impact, all AMD would have to do is remove 11um of Si from the back of a die prior to attaching a IHS. It would also have the effect of making a near mirror finish to remove more of the voids in the die IHS interface and that could help even more. BTW IIRC, both Intel and AMD when the dies were bare, coated the exposed die. That would increase the thermal resistance as much as any SOI layer, if not more. Frankly, it seems to be just a red herring. Pete