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To: Sarmad Y. Hermiz who wrote (228841)3/24/2007 8:46:32 PM
From: muzosiRead Replies (1) | Respond to of 275872
 
I think the delays in a collection of transistors and gates can be modeled accurately in simulations at design time. What is likely subject to error is leakage and switching speed. Is that correct ?

i'm not sure i understand. you can only calculate the delays by knowing switching speed. maybe you mean the rate of switching? ie toggle rate?

when (or while) one is designing for a process, someone has (is) also characterized(ing) the process ie making basic circuits and refining the transistor models to match the actual measurements so one hopes that one has very accurate transistor models which describe transistor performance, leakage etc.
actually that's one reason people make wafers with sram cells, ring oscillators, and other circuits while bringing up a process.