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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: misen who wrote (237495)	7/30/2007 1:31:43 AM
From: Petz	Respond to of 275872

re: cache redundancy does not fix all defects that occur in the cache There are of course critical areas of the cache that cannot sustain defects. Some of these are outside the rectangular blocks identified as L2 and L3, so wouldn't count in the area anyway. The rest has an insignificant die area. it is more susceptible to the presence of defects that are "killer" defects Are you talking about a very large defect or something else? As long as the defect is localized, I don't see why the row & column couldn't be disabled. Link please. Funny no one ever mentioned this in connection with Intel's oversized P4 caches. If you "guess" wrong on the defect density, you will either have a die size that is too large with unused redundancy or low yields due to not enough redundancy. It sounds to me like you are assuming that AMD is using EDAC to correct bit errors caused by defects. NOT! Or you are talking about the minute probability of multiple defects within a single cache. It's silly to think that AMD or Intel or anyone would have redundancy greater than the absolute minimum of allowing a single defect in each cache to be mapped out. If there is EDAC, it is on top of the defect isolation and is a function of noise margin, not defect elimination. You are correct that multiple defects in a single cache will result in a failure which is not considered in my simplified calculation. But this is a second order effect and couldn't reduce yield by more than 2%. Petz