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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (238802)	8/15/2007 10:56:04 AM
From: wbmw	Read Replies (1) \| Respond to of 275872

Re: IIRC, L3 in Barcelona is not strictly exclusive. It's actually a hybrid victim cache. Pure victim caches receive the implicit writebacks from the lower level cache (implicit writebacks happen when you fetch data and have to write back the oldest - called LRU - data in the cache set to memory), and rather than going to memory, the LRU gets written to the victim cache. AMD's L3 will have the option of having the core write directly to it, rather than to L2. There may be cases where the core is smart enough to know that the data won't be used again soon, so no reason to take up L2 space and write back data that will be used again.